MIPS: mips32/cache.S: store cache line size in t8 register

[karo-tx-uboot.git] / arch / mips / cpu / mips32 / cache.S

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 5ce0ec45fc3509fa81a27e0a5e7ea342d3ad1048..d3f156e4822a908738e9e96cdc793a937506b249 100644 (file)
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -3,23 +3,7 @@
  *
  *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <asm-offsets.h>
@@ -30,7 +14,11 @@
 #include <asm/addrspace.h>
 #include <asm/cacheops.h>
 
-#define RA             t8
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
+#define RA             t9
 
 /*
  * 16kB is the maximum size of instruction and data caches on MIPS 4K,
@@ -81,17 +69,17 @@ LEAF(mips_init_icache)
        /* clear tag to invalidate */
        PTR_LI          t0, INDEX_BASE
        PTR_ADDU        t1, t0, a1
-1:     cache_op        Index_Store_Tag_I t0
+1:     cache_op        INDEX_STORE_TAG_I t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
        /* fill once, so data field parity is correct */
        PTR_LI          t0, INDEX_BASE
-2:     cache_op        Fill t0
+2:     cache_op        FILL t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 2b
        /* invalidate again - prudent but not strictly neccessary */
        PTR_LI          t0, INDEX_BASE
-1:     cache_op        Index_Store_Tag_I t0
+1:     cache_op        INDEX_STORE_TAG_I t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
 9:     jr              ra
@@ -106,7 +94,7 @@ LEAF(mips_init_dcache)
        /* clear all tags */
        PTR_LI          t0, INDEX_BASE
        PTR_ADDU        t1, t0, a1
-1:     cache_op        Index_Store_Tag_D t0
+1:     cache_op        INDEX_STORE_TAG_D t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
        /* load from each line (in cached space) */
@@ -116,7 +104,7 @@ LEAF(mips_init_dcache)
        bne             t0, t1, 2b
        /* clear all tags */
        PTR_LI          t0, INDEX_BASE
-1:     cache_op        Index_Store_Tag_D t0
+1:     cache_op        INDEX_STORE_TAG_D t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
 9:     jr              ra
@@ -140,8 +128,7 @@ NESTED(mips_cache_reset, 0, ra)
        move    RA, ra
        li      t2, CONFIG_SYS_ICACHE_SIZE
        li      t3, CONFIG_SYS_DCACHE_SIZE
-       li      t4, CONFIG_SYS_CACHELINE_SIZE
-       move    t5, t4
+       li      t8, CONFIG_SYS_CACHELINE_SIZE
 
        li      v0, MIPS_MAX_CACHE_SIZE
 
@@ -168,7 +155,7 @@ NESTED(mips_cache_reset, 0, ra)
         * Initialize the I-cache first,
         */
        move    a1, t2
-       move    a2, t4
+       move    a2, t8
        PTR_LA  t7, mips_init_icache
        jalr    t7
 
@@ -176,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra)
         * then initialize D-cache.
         */
        move    a1, t3
-       move    a2, t5
+       move    a2, t8
        PTR_LA  t7, mips_init_dcache
        jalr    t7
 
@@ -224,7 +211,7 @@ LEAF(dcache_enable)
        mfc0    t0, CP0_CONFIG
        ori     t0, CONF_CM_CMASK
        xori    t0, CONF_CM_CMASK
-       ori     t0, CONF_CM_CACHABLE_NONCOHERENT
+       ori     t0, CONFIG_SYS_MIPS_CACHE_MODE
        mtc0    t0, CP0_CONFIG
        jr      ra
        END(dcache_enable)