Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / speed.c

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index d08a8d212d7ddc448bd7bfa2dc7f342a519fb3df..46ae80c4d819b244de758d60a28a09cd6095d4a5 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -86,6 +86,14 @@ void get_sys_info(sys_info_t *sys_info)
        mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
                        FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
                        & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+       /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
+        * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
+        * it uses 6.
+        */
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+       if (SVR_MAJ(get_svr()) >= 2)
+               mem_pll_rat *= 2;
+#endif
        if (mem_pll_rat > 2)
                sys_info->freq_ddrbus *= mem_pll_rat;
        else
@@ -122,7 +130,7 @@ void get_sys_info(sys_info_t *sys_info)
                sys_info->freq_processor[cpu] =
                         freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
        }
-#ifdef CONFIG_PPC_B4860
+#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
 #define FM1_CLK_SEL    0xe0000000
 #define FM1_CLK_SHIFT  29
 #else