*
* COPYRIGHT AMCC CORPORATION 2004
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier: GPL-2.0+
*/
/* define DEBUG for debugging output (obviously ;-)) */
#include <common.h>
#include <command.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/processor.h>
#include "ecc.h"
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
-
#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
do { \
u32 data; \
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+static void update_rdcc(void)
+{
+ u32 val;
+
+ /*
+ * Complete RDSS configuration as mentioned on page 7 of the AMCC
+ * PowerPC440SP/SPe DDR2 application note:
+ * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
+ *
+ * Or item #10 "10. Complete RDSS configuration" in chapter
+ * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
+ * manual.
+ */
+ mfsdram(SDRAM_RTSR, val);
+ if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
+ mfsdram(SDRAM_RDCC, val);
+ if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
+ val += 0x40000000;
+ mtsdram(SDRAM_RDCC, val);
+ }
+ }
+}
+#endif
+
#if defined(CONFIG_440)
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2
/*-----------------------------------------------------------------------------+
* Defines
*-----------------------------------------------------------------------------*/
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
#define SDRAM_DDR1 1
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
static void DQS_calibration_process(void);
#endif
#endif
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
static unsigned char spd_read(uchar chip, uint addr)
{
phys_size_t initdram(int board_type)
{
unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
- unsigned char spd0[MAX_SPD_BYTES];
- unsigned char spd1[MAX_SPD_BYTES];
- unsigned char *dimm_spd[MAXDIMMS];
unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
unsigned long num_dimm_banks; /* on board dimm banks */
unsigned long val;
num_dimm_banks = sizeof(iic0_dimm_addr);
- /*------------------------------------------------------------------
- * Set up an array of SPD matrixes.
- *-----------------------------------------------------------------*/
- dimm_spd[0] = spd0;
- dimm_spd[1] = spd1;
-
/*------------------------------------------------------------------
* Reset the DDR-SDRAM controller.
*-----------------------------------------------------------------*/
- mtsdr(SDR0_SRST, (0x80000000 >> 10));
+ mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
mtsdr(SDR0_SRST, 0x00000000);
/*
*/
/* switch to correct I2C bus */
- I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
/*------------------------------------------------------------------
* Clear out the serial presence detect buffers.
#else
program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
#endif
+ /*
+ * Now complete RDSS configuration as mentioned on page 7 of the AMCC
+ * PowerPC440SP/SPe DDR2 application note:
+ * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
+ */
+ update_rdcc();
#ifdef CONFIG_DDR_ECC
/*------------------------------------------------------------------
program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
#endif
+ /*
+ * Flush the dcache before removing the TLB with caches
+ * enabled. Otherwise this might lead to problems later on,
+ * e.g. while booting Linux (as seen on ICON-440SPe).
+ */
+ flush_dcache();
+
/*
* Now after initialization (auto-calibration and ECC generation)
* remove the TLB entries with caches enabled and program again with
unsigned char num_of_bytes;
unsigned char total_size;
- dimm_found = FALSE;
+ dimm_found = false;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
num_of_bytes = 0;
total_size = 0;
iic0_dimm_addr[dimm_num], total_size);
if ((num_of_bytes != 0) && (total_size != 0)) {
- dimm_populated[dimm_num] = TRUE;
- dimm_found = TRUE;
+ dimm_populated[dimm_num] = true;
+ dimm_found = true;
debug("DIMM slot %lu: populated\n", dimm_num);
} else {
- dimm_populated[dimm_num] = FALSE;
+ dimm_populated[dimm_num] = false;
debug("DIMM slot %lu: Not populated\n", dimm_num);
}
}
- if (dimm_found == FALSE) {
+ if (dimm_found == false) {
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
spd_ddr_init_hang ();
}
unsigned long dimm_type;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
+ if (dimm_populated[dimm_num] == true) {
dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
switch (dimm_type) {
case 1:
unsigned long attribute = 0;
unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
unsigned long bankcount;
- unsigned long ddrtype;
unsigned long val;
#ifdef CONFIG_DDR_ECC
- ecc_enabled = TRUE;
+ ecc_enabled = true;
#else
- ecc_enabled = FALSE;
+ ecc_enabled = false;
#endif
- dimm_32bit = FALSE;
- dimm_64bit = FALSE;
- buf0 = FALSE;
- buf1 = FALSE;
+ dimm_32bit = false;
+ dimm_64bit = false;
+ buf0 = false;
+ buf1 = false;
/*------------------------------------------------------------------
* Set memory controller options reg 1, SDRAM_MCOPT1.
/* test ecc support */
ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
if (ecc != 0x02) /* ecc not supported */
- ecc_enabled = FALSE;
+ ecc_enabled = false;
/* test bank count */
bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
else /* bank count = 8 */
mcopt1 |= SDRAM_MCOPT1_8_BANKS;
- /* test DDR type */
- ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
/* test for buffered/unbuffered, registered, differential clocks */
registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
if (registered == 1) { /* DDR2 always buffered */
/* TODO: what about above comments ? */
mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf0 = TRUE;
+ buf0 = true;
} else {
/* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
if ((attribute & 0x02) == 0x00) {
/* buffered not supported */
- buf0 = FALSE;
+ buf0 = false;
} else {
mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf0 = TRUE;
+ buf0 = true;
}
}
}
if (registered == 1) {
/* DDR2 always buffered */
mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf1 = TRUE;
+ buf1 = true;
} else {
if ((attribute & 0x02) == 0x00) {
/* buffered not supported */
- buf1 = FALSE;
+ buf1 = false;
} else {
mcopt1 |= SDRAM_MCOPT1_RDEN;
- buf1 = TRUE;
+ buf1 = true;
}
}
}
switch (data_width) {
case 72:
case 64:
- dimm_64bit = TRUE;
+ dimm_64bit = true;
break;
case 40:
case 32:
- dimm_32bit = TRUE;
+ dimm_32bit = true;
break;
default:
printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
}
}
- if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
+ if ((dimm_64bit == true) && (dimm_32bit == true)) {
printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
spd_ddr_init_hang ();
- }
- else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
+ } else if ((dimm_64bit == true) && (dimm_32bit == false)) {
mcopt1 |= SDRAM_MCOPT1_DMWD_64;
- } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
+ } else if ((dimm_64bit == false) && (dimm_32bit == true)) {
mcopt1 |= SDRAM_MCOPT1_DMWD_32;
} else {
printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
spd_ddr_init_hang ();
}
- if (ecc_enabled == TRUE)
+ if (ecc_enabled == true)
mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
else
mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
total_rank += dimm_rank;
total_dimm++;
if ((dimm_num == 0) && (total_dimm == 1))
- firstSlot = TRUE;
+ firstSlot = true;
else
- firstSlot = FALSE;
+ firstSlot = false;
}
}
if (dimm_type == SDRAM_DDR2) {
codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
- if ((total_dimm == 1) && (firstSlot == TRUE)) {
+ if ((total_dimm == 1) && (firstSlot == true)) {
if (total_rank == 1) { /* PUUU */
codt |= CALC_ODT_R(0);
modt0 = CALC_ODT_W(0);
modt2 = 0x00000000;
modt3 = 0x00000000;
}
- } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
+ } else if ((total_dimm == 1) && (firstSlot != true)) {
if (total_rank == 1) { /* UUPU */
codt |= CALC_ODT_R(2);
modt0 = 0x00000000;
* the dimm modules installed.
*-----------------------------------------------------------------*/
t_wr_ns = 0;
- cas_2_0_available = TRUE;
- cas_2_5_available = TRUE;
- cas_3_0_available = TRUE;
- cas_4_0_available = TRUE;
- cas_5_0_available = TRUE;
+ cas_2_0_available = true;
+ cas_2_5_available = true;
+ cas_3_0_available = true;
+ cas_4_0_available = true;
+ cas_5_0_available = true;
max_2_0_tcyc_ns_x_100 = 10;
max_2_5_tcyc_ns_x_100 = 10;
max_3_0_tcyc_ns_x_100 = 10;
max_4_0_tcyc_ns_x_100 = 10;
max_5_0_tcyc_ns_x_100 = 10;
- sdram_ddr1 = TRUE;
+ sdram_ddr1 = true;
/* loop through all the DIMM slots on the board */
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE) {
if (dimm_populated[dimm_num] == SDRAM_DDR1)
- sdram_ddr1 = TRUE;
+ sdram_ddr1 = true;
else
- sdram_ddr1 = FALSE;
+ sdram_ddr1 = false;
- /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
} else {
if (cas_index != 0)
cas_index++;
- cas_4_0_available = FALSE;
+ cas_4_0_available = false;
}
if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
} else {
if (cas_index != 0)
cas_index++;
- cas_3_0_available = FALSE;
+ cas_3_0_available = false;
}
if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
} else {
if (cas_index != 0)
cas_index++;
- cas_2_5_available = FALSE;
+ cas_2_5_available = false;
}
if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
} else {
if (cas_index != 0)
cas_index++;
- cas_2_0_available = FALSE;
+ cas_2_0_available = false;
}
} else {
/*
} else {
if (cas_index != 0)
cas_index++;
- cas_5_0_available = FALSE;
+ cas_5_0_available = false;
}
if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
} else {
if (cas_index != 0)
cas_index++;
- cas_4_0_available = FALSE;
+ cas_4_0_available = false;
}
if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
} else {
if (cas_index != 0)
cas_index++;
- cas_3_0_available = FALSE;
+ cas_3_0_available = false;
}
}
}
debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
- if (sdram_ddr1 == TRUE) { /* DDR1 */
- if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
+ if (sdram_ddr1 == true) { /* DDR1 */
+ if ((cas_2_0_available == true) &&
+ (sdram_freq <= cycle_2_0_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
*selected_cas = DDR_CAS_2;
- } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
+ } else if ((cas_2_5_available == true) &&
+ (sdram_freq <= cycle_2_5_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
*selected_cas = DDR_CAS_2_5;
- } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
+ } else if ((cas_3_0_available == true) &&
+ (sdram_freq <= cycle_3_0_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
*selected_cas = DDR_CAS_3;
} else {
debug("cas_3_0_available=%d\n", cas_3_0_available);
debug("cas_4_0_available=%d\n", cas_4_0_available);
debug("cas_5_0_available=%d\n", cas_5_0_available);
- if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
+ if ((cas_3_0_available == true) &&
+ (sdram_freq <= cycle_3_0_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
*selected_cas = DDR_CAS_3;
- } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
+ } else if ((cas_4_0_available == true) &&
+ (sdram_freq <= cycle_4_0_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
*selected_cas = DDR_CAS_4;
- } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
+ } else if ((cas_5_0_available == true) &&
+ (sdram_freq <= cycle_5_0_clk)) {
mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
*selected_cas = DDR_CAS_5;
} else {
}
}
- if (sdram_ddr1 == TRUE)
+ if (sdram_ddr1 == true)
mmode |= SDRAM_MMODE_WR_DDR1;
else {
t_wpc_ns = 0;
t_wtr_ns = 0;
t_rpc_ns = 0;
- sdram_ddr1 = TRUE;
+ sdram_ddr1 = true;
/* loop through all the DIMM slots on the board */
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
/* If a dimm is installed in a particular slot ... */
if (dimm_populated[dimm_num] != SDRAM_NONE) {
if (dimm_populated[dimm_num] == SDRAM_DDR2)
- sdram_ddr1 = TRUE;
+ sdram_ddr1 = true;
else
- sdram_ddr1 = FALSE;
+ sdram_ddr1 = false;
t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
break;
}
- if (sdram_ddr1 == TRUE) { /* DDR1 */
+ if (sdram_ddr1 == true) { /* DDR1 */
if (sdram_freq < 200000000) {
sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
unsigned long val;
long rffd_average;
long max_start;
- long min_end;
- unsigned long begin_rqfd[MAXRANKS];
- unsigned long begin_rffd[MAXRANKS];
- unsigned long end_rqfd[MAXRANKS];
- unsigned long end_rffd[MAXRANKS];
- char window_found;
unsigned long dlycal;
unsigned long dly_val;
unsigned long max_pass_length;
unsigned char fail_found;
unsigned char pass_found;
#if !defined(CONFIG_DDR_RQDC_FIXED)
+ int window_found;
u32 rqdc_reg;
u32 rqfd;
u32 rqfd_start;
#endif /* CONFIG_DDR_RQDC_FIXED */
max_start = 0;
- min_end = 0;
- begin_rqfd[0] = 0;
- begin_rffd[0] = 0;
- begin_rqfd[1] = 0;
- begin_rffd[1] = 0;
- end_rqfd[0] = 0;
- end_rffd[0] = 0;
- end_rqfd[1] = 0;
- end_rffd[1] = 0;
- window_found = FALSE;
max_pass_length = 0;
max_start = 0;
current_pass_length = 0;
current_fail_length = 0;
current_start = 0;
- window_found = FALSE;
- fail_found = FALSE;
- pass_found = FALSE;
+ fail_found = false;
+ pass_found = false;
/*
* get the delay line calibration register value
* See if the rffd value passed.
*-----------------------------------------------------------------*/
if (short_mem_test()) {
- if (fail_found == TRUE) {
- pass_found = TRUE;
+ if (fail_found == true) {
+ pass_found = true;
if (current_pass_length == 0)
current_start = rffd;
current_fail_length++;
if (current_fail_length >= (dly_val >> 2)) {
- if (fail_found == FALSE) {
- fail_found = TRUE;
- } else if (pass_found == TRUE) {
- window_found = TRUE;
+ if (fail_found == false)
+ fail_found = true;
+ else if (pass_found == true)
break;
- }
}
}
} /* for rffd */
current_pass_length = 0;
current_fail_length = 0;
current_start = 0;
- window_found = FALSE;
- fail_found = FALSE;
- pass_found = FALSE;
+ window_found = false;
+ fail_found = false;
+ pass_found = false;
for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
mfsdram(SDRAM_RQDC, rqdc_reg);
* See if the rffd value passed.
*-----------------------------------------------------------------*/
if (short_mem_test()) {
- if (fail_found == TRUE) {
- pass_found = TRUE;
+ if (fail_found == true) {
+ pass_found = true;
if (current_pass_length == 0)
current_start = rqfd;
current_pass_length = 0;
current_fail_length++;
- if (fail_found == FALSE) {
- fail_found = TRUE;
- } else if (pass_found == TRUE) {
- window_found = TRUE;
+ if (fail_found == false) {
+ fail_found = true;
+ } else if (pass_found == true) {
+ window_found = true;
break;
}
}
/*------------------------------------------------------------------
* Make sure we found the valid read passing window. Halt if not
*-----------------------------------------------------------------*/
- if (window_found == FALSE) {
+ if (window_found == false) {
if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
putc('\b');
putc(slash[loopi++ % 8]);
blank_string(strlen(str));
#endif /* CONFIG_DDR_RQDC_FIXED */
- /*
- * Now complete RDSS configuration as mentioned on page 7 of the AMCC
- * PowerPC440SP/SPe DDR2 application note:
- * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
- */
- mfsdram(SDRAM_RTSR, val);
- if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
- mfsdram(SDRAM_RDCC, val);
- if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
- val += 0x40000000;
- mtsdram(SDRAM_RDCC, val);
- }
- }
-
mfsdram(SDRAM_DLCR, val);
debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
mfsdram(SDRAM_RQDC, val);
mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
SDRAM_MCOPT1_MCHK_NON);
- window_found = FALSE;
- begin_found[0] = FALSE;
- end_found[0] = FALSE;
- search_end[0] = FALSE;
- begin_found[1] = FALSE;
- end_found[1] = FALSE;
- search_end[1] = FALSE;
+ window_found = false;
+ begin_found[0] = false;
+ end_found[0] = false;
+ search_end[0] = false;
+ begin_found[1] = false;
+ end_found[1] = false;
+ search_end[1] = false;
for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
* See if the rffd value passed.
*-----------------------------------------------------------------*/
if (i < NUMMEMTESTS) {
- if ((end_found[dimm_num] == FALSE) &&
- (search_end[dimm_num] == TRUE)) {
- end_found[dimm_num] = TRUE;
+ if ((end_found[dimm_num] == false) &&
+ (search_end[dimm_num] == true)) {
+ end_found[dimm_num] = true;
}
- if ((end_found[0] == TRUE) &&
- (end_found[1] == TRUE))
+ if ((end_found[0] == true) &&
+ (end_found[1] == true))
break;
} else {
- if (begin_found[dimm_num] == FALSE) {
- begin_found[dimm_num] = TRUE;
- search_end[dimm_num] = TRUE;
+ if (begin_found[dimm_num] == false) {
+ begin_found[dimm_num] = true;
+ search_end[dimm_num] = true;
}
}
} else {
- begin_found[dimm_num] = TRUE;
- end_found[dimm_num] = TRUE;
+ begin_found[dimm_num] = true;
+ end_found[dimm_num] = true;
}
}
- if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
- window_found = TRUE;
+ if ((begin_found[0] == true) && (begin_found[1] == true))
+ window_found = true;
/*------------------------------------------------------------------
* Make sure we found the valid read passing window. Halt if not
*-----------------------------------------------------------------*/
- if (window_found == FALSE) {
+ if (window_found == false) {
printf("ERROR: Cannot determine a common read delay for the "
"DIMM(s) installed.\n");
spd_ddr_init_hang ();
#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
+ /*
+ * Now complete RDSS configuration as mentioned on page 7 of the AMCC
+ * PowerPC440SP/SPe DDR2 application note:
+ * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
+ */
+ update_rdcc();
+
#if defined(CONFIG_DDR_ECC)
do_program_ecc(0);
#endif /* defined(CONFIG_DDR_ECC) */
PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
#endif /* defined(DEBUG) */
}
-
-#endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
projects / karo-tx-uboot.git / blobdiff