#endif
extern ulong __init_end;
-extern ulong __bss_end__;
+extern ulong __bss_end;
ulong monitor_flash_len;
#if defined(CONFIG_CMD_BEDBUG)
/***********************************************************************/
-void __board_add_ram_info(int use_default)
+static void __board_add_ram_info(int use_default)
{
/* please define platform specific board_add_ram_info() */
}
void board_add_ram_info(int)
__attribute__ ((weak, alias("__board_add_ram_info")));
-int __board_flash_wp_on(void)
+static int __board_flash_wp_on(void)
{
/*
* Most flashes can't be detected when write protection is enabled,
int board_flash_wp_on(void)
__attribute__ ((weak, alias("__board_flash_wp_on")));
-void __cpu_secondary_init_r(void)
+static void __cpu_secondary_init_r(void)
{
}
/***********************************************************************/
#if defined(CONFIG_WATCHDOG)
-static int init_func_watchdog_init(void)
+int init_func_watchdog_init(void)
{
puts(" Watchdog enabled\n");
WATCHDOG_RESET();
return 0;
}
-#define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
-
-static int init_func_watchdog_reset(void)
+int init_func_watchdog_reset(void)
{
WATCHDOG_RESET();
return 0;
}
-
-#define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
-#else
-#define INIT_FUNC_WATCHDOG_INIT /* undef */
-#define INIT_FUNC_WATCHDOG_RESET /* undef */
#endif /* CONFIG_WATCHDOG */
/*
* Initialization sequence
*/
-init_fnc_t *init_sequence[] = {
+static init_fnc_t *init_sequence[] = {
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
probecpu,
#endif
#ifdef CONFIG_POST
post_init_f,
#endif
- INIT_FUNC_WATCHDOG_RESET init_func_ram,
+ INIT_FUNC_WATCHDOG_RESET
+ init_func_ram,
#if defined(CONFIG_SYS_DRAM_TEST)
testdram,
#endif /* CONFIG_SYS_DRAM_TEST */
#endif
}
+static int __fixup_cpu(void)
+{
+ return 0;
+}
+
+int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu")));
+
/*
* This is the first part of the initialization sequence that is
* implemented in C, but still running from ROM.
#ifdef CONFIG_POST
post_bootmode_init();
- post_run(NULL, POST_ROM | post_bootmode_get(0));
+ post_run(NULL, POST_ROM | post_bootmode_get(NULL));
#endif
WATCHDOG_RESET();
* - monitor code
* - board info struct
*/
- len = (ulong)&__bss_end__ - CONFIG_SYS_MONITOR_BASE;
+ len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
/*
* Subtract specified amount of memory to hide so that it won't
* We need to make sure the location we intend to put secondary core
* boot code is reserved and not used by any part of u-boot
*/
- if (addr > determine_mp_bootpg()) {
- addr = determine_mp_bootpg();
+ if (addr > determine_mp_bootpg(NULL)) {
+ addr = determine_mp_bootpg(NULL);
debug("Reserving MP boot page to %08lx\n", addr);
}
#endif
addr_sp -= 16;
addr_sp &= ~0xF;
s = (ulong *) addr_sp;
- *s-- = 0;
- *s-- = 0;
- addr_sp = (ulong) s;
+ *s = 0; /* Terminate back chain */
+ *++s = 0; /* NULL return address */
debug("Stack Pointer at: %08lx\n", addr_sp);
/*
#endif
#if defined(CONFIG_MPC8220)
bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
- bd->bi_inpfreq = gd->inp_clk;
+ bd->bi_inpfreq = gd->arch.inp_clk;
bd->bi_pcifreq = gd->pci_clk;
- bd->bi_vcofreq = gd->vco_clk;
- bd->bi_pevfreq = gd->pev_clk;
- bd->bi_flbfreq = gd->flb_clk;
+ bd->bi_vcofreq = gd->arch.vco_clk;
+ bd->bi_pevfreq = gd->arch.pev_clk;
+ bd->bi_flbfreq = gd->arch.flb_clk;
/* store bootparam to sram (backward compatible), here? */
{
*sram++ = gd->ram_size;
*sram++ = gd->bus_clk;
- *sram++ = gd->inp_clk;
+ *sram++ = gd->arch.inp_clk;
*sram++ = gd->cpu_clk;
- *sram++ = gd->vco_clk;
- *sram++ = gd->flb_clk;
+ *sram++ = gd->arch.vco_clk;
+ *sram++ = gd->arch.flb_clk;
*sram++ = 0xb8c3ba11; /* boot signature */
}
#endif
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
#if defined(CONFIG_CPM2)
- bd->bi_cpmfreq = gd->cpm_clk;
- bd->bi_brgfreq = gd->brg_clk;
- bd->bi_sccfreq = gd->scc_clk;
- bd->bi_vco = gd->vco_out;
+ bd->bi_cpmfreq = gd->arch.cpm_clk;
+ bd->bi_brgfreq = gd->arch.brg_clk;
+ bd->bi_sccfreq = gd->arch.scc_clk;
+ bd->bi_vco = gd->arch.vco_out;
#endif /* CONFIG_CPM2 */
#if defined(CONFIG_MPC512X)
- bd->bi_ipsfreq = gd->ips_clk;
+ bd->bi_ipsfreq = gd->arch.ips_clk;
#endif /* CONFIG_MPC512X */
#if defined(CONFIG_MPC5xxx)
- bd->bi_ipbfreq = gd->ipb_clk;
+ bd->bi_ipbfreq = gd->arch.ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
#endif /* CONFIG_MPC5xxx */
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/*
- * The gd->cpu pointer is set to an address in flash before relocation.
- * We need to update it to point to the same CPU entry in RAM.
+ * The gd->arch.cpu pointer is set to an address in flash before
+ * relocation. We need to update it to point to the same CPU entry
+ * in RAM.
+ */
+ gd->arch.cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
+
+ /*
+ * If we didn't know the cpu mask & # cores, we can save them of
+ * now rather than 'computing' them constantly
*/
- gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
+ fixup_cpu();
#endif
#ifdef CONFIG_SYS_EXTRA_ENV_RELOC
gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE;
#endif
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
flash_size = 0;
} else if ((flash_size = flash_init()) > 0) {
#ifdef CONFIG_SYS_FLASH_CHECKSUM
- char *s;
-
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
- s = getenv("flashchecksum");
- if (s && (*s == 'y')) {
+ if (getenv_yesno("flashchecksum") == 1) {
printf(" CRC: %08X",
crc32(0,
(const unsigned char *)
* "i2cfast" into account
*/
{
- char *s = getenv("i2cfast");
-
- if (s && ((*s == 'y') || (*s == 'Y'))) {
+ if (getenv_yesno("i2cfast") == 1) {
bd->bi_iic_fast[0] = 1;
bd->bi_iic_fast[1] = 1;
}
projects / karo-tx-uboot.git / blobdiff