imported Freescale specific U-Boot additions for i.MX28,... release L2.6.31_10.08.01

[karo-tx-uboot.git] / board / cpu86 / cpu86.c

diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c
index 3eb5b354264d792360f8b32d4b84d6350dbc6dfa..bc7ebfea183c2ead3001babd497c4cdbaed97349 100755 (executable)
--- a/board/cpu86/cpu86.c
+++ b/board/cpu86/cpu86.c
@@ -225,7 +225,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
         */
        maxsize = (1 + (~orx | 0x7fff)) / 2;
 
-       /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+       /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
         * we are configuring CS1 if base != 0
         */
        sdmr_ptr = &memctl->memc_psdmr;
@@ -250,7 +250,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
         *  accessing the SDRAM with a single-byte transaction."
         *
         * The appropriate BRx/ORx registers have already been set when we
-        * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+        * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
         */
 
        *sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -261,7 +261,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
                *base = c;
 
        *sdmr_ptr = sdmr | PSDMR_OP_MRW;
-       *(base + CFG_MRS_OFFS) = c;     /* setting MR on address lines */
+       *(base + CONFIG_SYS_MRS_OFFS) = c;      /* setting MR on address lines */
 
        *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
        *base = c;
@@ -273,49 +273,48 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
        return (size);
 }
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMR;
+       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
        ulong size8, size9;
 #endif
        long psize;
 
        psize = 32 * 1024 * 1024;
 
-       memctl->memc_mptpr = CFG_MPTPR;
-       memctl->memc_psrt = CFG_PSRT;
+       memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+       memctl->memc_psrt = CONFIG_SYS_PSRT;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
        /* 60x SDRAM setup:
         */
-       size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-                         (uchar *) CFG_SDRAM_BASE);
-       size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-                         (uchar *) CFG_SDRAM_BASE);
+       size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+                         (uchar *) CONFIG_SYS_SDRAM_BASE);
+       size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+                         (uchar *) CONFIG_SYS_SDRAM_BASE);
 
        if (size8 < size9) {
                psize = size9;
                printf ("(60x:9COL) ");
        } else {
-               psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-                                 (uchar *) CFG_SDRAM_BASE);
+               psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+                                 (uchar *) CONFIG_SYS_SDRAM_BASE);
                printf ("(60x:8COL) ");
        }
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
        icache_enable ();
 
        return (psize);
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_DOC)
-extern void doc_probe (ulong physadr);
+#if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-       doc_probe (CFG_DOC_BASE);
+       doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif