/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
#include "pci405.h"
-/* ------------------------------------------------------------------------- */
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/
+unsigned long fpga_done_state(void);
+unsigned long fpga_init_state(void);
+
#if 0
#define FPGA_DEBUG
#endif
+/* predefine these here */
+#define FPGA_DONE_STATE (fpga_done_state())
+#define FPGA_INIT_STATE (fpga_init_state())
+
/* fpga configuration data - generated by bin2cc */
const unsigned char fpgadata[] =
{
*/
#include "../common/fpga.c"
+#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_DONE)
+#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_DONE_V12)
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_INIT)
+#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_INIT_V12)
+
+
+int board_revision(void)
+{
+ unsigned long cntrl0Reg;
+ unsigned long value;
+
+ /*
+ * Get version of PCI405 board from GPIO's
+ */
+
+ /*
+ * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+ */
+ cntrl0Reg = mfdcr(cntrl0);
+ mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+ udelay(1000); /* wait some time before reading input */
+ value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
+
+ /*
+ * Restore GPIO settings
+ */
+ mtdcr(cntrl0, cntrl0Reg);
+
+ switch (value) {
+ case 0x00180000:
+ /* CS2==1 && CS3==1 -> version 1.0 and 1.1 */
+ return 1;
+ case 0x00080000:
+ /* CS2==0 && CS3==1 -> version 1.2 */
+ return 2;
+#if 0 /* not yet manufactured ! */
+ case 0x00100000:
+ /* CS2==1 && CS3==0 -> version 1.3 */
+ return 3;
+ case 0x00000000:
+ /* CS2==0 && CS3==0 -> version 1.4 */
+ return 4;
+#endif
+ default:
+ /* should not be reached! */
+ return 0;
+ }
+}
+
+
+unsigned long fpga_done_state(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ if (gd->board_type < 2) {
+ return FPGA_DONE_STATE_V11;
+ } else {
+ return FPGA_DONE_STATE_V12;
+ }
+}
+
+
+unsigned long fpga_init_state(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ if (gd->board_type < 2) {
+ return FPGA_INIT_STATE_V11;
+ } else {
+ return FPGA_INIT_STATE_V12;
+ }
+}
int board_early_init_f (void)
{
unsigned long cntrl0Reg;
+ /*
+ * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
+ */
+ out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
+ out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
+ out32(GPIO0_OR, 0); /* pull prg low */
+
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* IRQ 16 405GP internally generated; active low; level sensitive
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00008000);
+ /*
+ * Setup GPIO pins (CS6+CS7 as GPIO)
+ */
+ mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
*/
*/
dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+ if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
*magic = 0; /* clear pci reconfig magic again */
}
+#if 1 /* test-only */
+ /*
+ * Decrease PLB latency timeout and reduce priority of the PCI bridge master
+ */
+#define PCI0_BRDGOPT1 0x4a
+ pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
+/* pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60); */
+
+#define plb0_acr 0x87
+ /*
+ * Enable fairness and high bus utilization
+ */
+ mtdcr(plb0_acr, 0x98000000);
+
+#if 0 /* test-only */
+ printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */
+/* mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000); */
+ mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000);
+#endif
+ /* printf("CCR0=%08x\n", mfspr(ccr0));*/ /* test-only */
+#endif
+
free(dst);
return (0);
}
int checkboard (void)
{
+ DECLARE_GLOBAL_DATA_PTR;
+
unsigned char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
} else {
puts (str);
}
- putc ('\n');
+
+ gd->board_type = board_revision();
+ printf(" (Rev 1.%ld", gd->board_type);
+
+ if (gd->board_type >= 2) {
+ unsigned long cntrl0Reg;
+ unsigned long value;
+
+ /*
+ * Setup GPIO pins (Trace/GPIO1 to GPIO)
+ */
+ cntrl0Reg = mfdcr(cntrl0);
+ mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
+ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000);
+ udelay(1000); /* wait some time before reading input */
+ value = in32(GPIO0_IR) & 0x40000000; /* get config bits */
+ if (value) {
+ puts(", 33 MHz PCI");
+ } else {
+ puts(", 66 Mhz PCI");
+ }
+ }
+
+ puts(")\n");
return 0;
}
projects / karo-tx-uboot.git / blobdiff