#include <command.h>
#include <malloc.h>
#include <asm/m5249.h>
+#include <asm/io.h>
/* Prototypes */
/* predefine these here for FPGA programming (before including fpga.c) */
#define SET_FPGA(data) mbar2_writeLong(MCFSIM_GPIO1_OUT, data)
-#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_DONE)
-#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_INIT)
+#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_INIT)
#define FPGA_PROG_ACTIVE_HIGH /* on this platform is PROG active high! */
#define out32(a,b) /* nothing to do (gpio already configured) */
/*
* Set LED on
*/
- val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED;
+ val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
return 0;
};
-long int initdram (int board_type) {
+phys_size_t initdram (int board_type) {
unsigned long junk = 0xa5a59696;
/*
* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
*/
-#ifdef CFG_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
/*
* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
*/
mbar_writeShort(MCFSIM_DCR, 0x8239);
-#elif CFG_PLL_BYPASS
+#elif CONFIG_SYS_PLL_BYPASS
/*
* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
/** Precharge sequence **/
mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
- *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
+ out_be32((void *)0, junk); /* write to a memory location to init. precharge */
udelay(0x10); /* Allow several Precharge cycles */
/** Refresh Sequence **/
/** Mode Register initialization **/
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
- *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
+ out_be32((void *)0x800, junk); /* Access RAM to initialize the mode register */
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
int i;
uchar buf[8];
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
addr = simple_strtol (argv[1], NULL, 16);
- printf("iprobe looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
+ printf("i2c probe looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
for (;;) {
i2c_probe(addr);
}
U_BOOT_CMD(
iploop, 2, 1, do_iploop,
- "iploop - iprobe loop <addr>\n",
- NULL
- );
+ "i2c probe loop <addr>",
+ ""
+);
/*
*/
{
uchar buf[8];
- *(volatile ushort *)0xe0000000 = 0x4000;
+ out_be16((void *)0xe0000000, 0x4000);
udelay(5000); /* wait for 5ms */
}
U_BOOT_CMD(
codec, 1, 1, do_codec,
- "codec - Enable codec\n",
- NULL
- );
+ "Enable codec",
+ ""
+);
/*
*/
}
U_BOOT_CMD(
saa, 5, 1, do_saa,
- "saa - Write to SAA1064 <addr> <instr> <cntrl> <data>\n",
- NULL
- );
+ "Write to SAA1064 <addr> <instr> <cntrl> <data>",
+ ""
+);
/*
*/
}
U_BOOT_CMD(
iwrite, 6, 1, do_iwrite,
- "iwrite - Write n bytes to I2C-device\n",
- "addr cnt data0 ... datan\n"
- );
+ "Write n bytes to I2C-device",
+ "addr cnt data0 ... datan"
+);
/*
*/
}
U_BOOT_CMD(
iread, 3, 1, do_iread,
- "iread - Read from I2C <addr> <cnt>\n",
- NULL
- );
+ "Read from I2C <addr> <cnt>",
+ ""
+);
/*
*/
}
U_BOOT_CMD(
ireadl, 2, 1, do_ireadl,
- "ireadl - Read-loop from I2C <addr>\n",
- NULL
- );
+ "Read-loop from I2C <addr>",
+ ""
+);
#endif