karo: merge with Ka-Ro specific tree for secure boot support

[karo-tx-uboot.git] / board / freescale / mx6sabresd / mx6sabresd.c

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 2f7198d3bfdfc0b438ec185973d62dcb3dc45156..215faa98fac2247cd268f471f29fabf605a3329c 100644 (file)
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -85,7 +85,7 @@ static iomux_v3_cfg_t const enet_pads[] = {
        MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
        /* AR8031 PHY Reset */
-       MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_ENET_CRS_DV__GPIO1_IO25,
 };
 
 static void setup_iomux_enet(void)
@@ -109,7 +109,7 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
        MX6_PAD_NANDF_D5__SD2_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_NANDF_D6__SD2_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_NANDF_D7__SD2_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+       MX6_PAD_NANDF_D2__GPIO2_IO02, /* CD */
 };
 
 static iomux_v3_cfg_t const usdhc3_pads[] = {
@@ -123,7 +123,7 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
        MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+       MX6_PAD_NANDF_D0__GPIO2_IO00, /* CD */
 };
 
 static iomux_v3_cfg_t const usdhc4_pads[] = {
@@ -143,40 +143,40 @@ static iomux_v3_cfg_t const ecspi1_pads[] = {
        MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
        MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
        MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-       MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_KEY_ROW1__GPIO4_IO09,
 };
 
 static iomux_v3_cfg_t const rgb_pads[] = {
-       MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+       MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+       MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
+       MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
+       MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04,
+       MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+       MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+       MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+       MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+       MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+       MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+       MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+       MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+       MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+       MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+       MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+       MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+       MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+       MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+       MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+       MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+       MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
+       MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
+       MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
+       MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
+       MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
+       MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
+       MX6_PAD_SD1_DAT3__GPIO1_IO21,
 };
 
 static void enable_rgb(struct display_info_t const *dev)
@@ -204,8 +204,8 @@ static void setup_spi(void)
 }
 
 iomux_v3_cfg_t const pcie_pads[] = {
-       MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),        /* POWER */
-       MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),        /* RESET */
+       MX6_PAD_EIM_D19__GPIO3_IO19,    /* POWER */
+       MX6_PAD_GPIO_17__GPIO7_IO12,    /* RESET */
 };
 
 static void setup_pcie(void)
@@ -543,12 +543,12 @@ int board_eth_init(bd_t *bis)
 #define UCTRL_PWR_POL          (1 << 9)
 
 static iomux_v3_cfg_t const usb_otg_pads[] = {
-       MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
-       MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_EIM_D22__USB_OTG_PWR,
+       MX6_PAD_ENET_RX_ER__USB_OTG_ID,
 };
 
 static iomux_v3_cfg_t const usb_hc1_pads[] = {
-       MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_ENET_TXD1__GPIO1_IO29,
 };
 
 static void setup_usb(void)