#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA)
-#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_GPIO (MXS_PAD_3V3 | MXS_PAD_PULLUP)
+#define LED_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define TSC_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define SSP0_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define SSP2_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define GPMI_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define ENET_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define EMI_PAD_CTRL (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define GPIO_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define UART_PAD_CTRL (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
static iomux_cfg_t tx28_stk5_pads[] = {
/* LED */
- MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
-
- /* framebuffer */
- MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
- MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
- MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
- MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
- MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD,
+ MX28_PAD_ENET0_RXD3__GPIO_4_10 | LED_PAD_CTRL,
/* DUART pads */
- MX28_PAD_PWM0__GPIO_3_16 | MUX_CONFIG_GPIO,
- MX28_PAD_PWM1__GPIO_3_17 | MUX_CONFIG_GPIO,
- MX28_PAD_I2C0_SCL__GPIO_3_24 | MUX_CONFIG_GPIO,
- MX28_PAD_I2C0_SDA__GPIO_3_25 | MUX_CONFIG_GPIO,
-
- MX28_PAD_AUART0_RTS__DUART_TX,
- MX28_PAD_AUART0_CTS__DUART_RX,
- MX28_PAD_AUART0_TX__DUART_RTS,
- MX28_PAD_AUART0_RX__DUART_CTS,
+ MX28_PAD_PWM0__GPIO_3_16 | GPIO_PAD_CTRL, /* LCD backlight */
+ MX28_PAD_PWM1__GPIO_3_17 | GPIO_PAD_CTRL,
+ /* pads for selected console UART */
+#if CONFIG_CONS_INDEX == 0
+ MX28_PAD_AUART0_RX__DUART_CTS | UART_PAD_CTRL,
+ MX28_PAD_AUART0_TX__DUART_RTS | UART_PAD_CTRL,
+ MX28_PAD_AUART0_CTS__DUART_RX | UART_PAD_CTRL,
+ MX28_PAD_AUART0_RTS__DUART_TX | UART_PAD_CTRL,
+#elif CONFIG_CONS_INDEX == 1
+ MX28_PAD_AUART1_RX__AUART1_RX | UART_PAD_CTRL,
+ MX28_PAD_AUART1_TX__AUART1_TX | UART_PAD_CTRL,
+ MX28_PAD_AUART1_CTS__AUART1_CTS | UART_PAD_CTRL,
+ MX28_PAD_AUART1_RTS__AUART1_RTS | UART_PAD_CTRL,
+#elif CONFIG_CONS_INDEX == 2
+ MX28_PAD_AUART3_RX__AUART3_RX | UART_PAD_CTRL,
+ MX28_PAD_AUART3_TX__AUART3_TX | UART_PAD_CTRL,
+ MX28_PAD_AUART3_CTS__AUART3_CTS | UART_PAD_CTRL,
+ MX28_PAD_AUART3_RTS__AUART3_RTS | UART_PAD_CTRL,
+#endif
/* EMI */
- MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D00__EMI_DATA0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D01__EMI_DATA1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D02__EMI_DATA2 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D03__EMI_DATA3 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D04__EMI_DATA4 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D05__EMI_DATA5 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D06__EMI_DATA6 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D07__EMI_DATA7 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D08__EMI_DATA8 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D09__EMI_DATA9 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D10__EMI_DATA10 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D11__EMI_DATA11 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D12__EMI_DATA12 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D13__EMI_DATA13 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D14__EMI_DATA14 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_D15__EMI_DATA15 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | EMI_PAD_CTRL,
+ MX28_PAD_EMI_CLK__EMI_CLK | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | EMI_PAD_CTRL,
- MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A00__EMI_ADDR0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_BA0__EMI_BA0 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_BA1__EMI_BA1 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_BA2__EMI_BA2 | EMI_PAD_CTRL,
+ MX28_PAD_EMI_CASN__EMI_CASN | EMI_PAD_CTRL,
+ MX28_PAD_EMI_RASN__EMI_RASN | EMI_PAD_CTRL,
+ MX28_PAD_EMI_WEN__EMI_WEN | EMI_PAD_CTRL,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | EMI_PAD_CTRL,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | EMI_PAD_CTRL,
+ MX28_PAD_EMI_CKE__EMI_CKE | EMI_PAD_CTRL,
/* FEC pads */
- MX28_PAD_PWM4__GPIO_3_29 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RX_EN__GPIO_4_2 | MUX_CONFIG_ENET, /* COL/CRS_DV/MODE2 */
- MX28_PAD_ENET0_RXD0__GPIO_4_3 | MUX_CONFIG_ENET, /* RXD0/MODE0 */
- MX28_PAD_ENET0_RXD1__GPIO_4_4 | MUX_CONFIG_ENET, /* RXD1/MODE1 */
- MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | MUX_CONFIG_ENET, /* nINT/TX_ER/TXD4 */
- MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+ MX28_PAD_PWM4__GPIO_3_29 | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_MDC__ENET0_MDC | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_RX_EN__GPIO_4_2 | ENET_PAD_CTRL, /* COL/CRS_DV/MODE2 */
+ MX28_PAD_ENET0_RXD0__GPIO_4_3 | ENET_PAD_CTRL, /* RXD0/MODE0 */
+ MX28_PAD_ENET0_RXD1__GPIO_4_4 | ENET_PAD_CTRL, /* RXD1/MODE1 */
+ MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | ENET_PAD_CTRL, /* nINT/TX_ER/TXD4 */
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | ENET_PAD_CTRL,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | ENET_PAD_CTRL,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | ENET_PAD_CTRL,
/* MMC pads */
- MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | SSP0_PAD_CTRL,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | SSP0_PAD_CTRL,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | SSP0_PAD_CTRL,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | SSP0_PAD_CTRL,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | SSP0_PAD_CTRL,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | GPIO_PAD_CTRL,
+ MX28_PAD_SSP0_SCK__SSP0_SCK | SSP0_PAD_CTRL,
/* GPMI pads */
- MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDN__GPMI_RDN | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D00__GPMI_D0 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D01__GPMI_D1 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D02__GPMI_D2 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D03__GPMI_D3 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D04__GPMI_D4 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D05__GPMI_D5 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D06__GPMI_D6 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_D07__GPMI_D7 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_RDN__GPMI_RDN | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_WRN__GPMI_WRN | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_ALE__GPMI_ALE | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_CLE__GPMI_CLE | GPMI_PAD_CTRL,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN | GPMI_PAD_CTRL,
+
+ /* maybe used for EDT-FT5x06 */
+ MX28_PAD_SSP0_DATA5__GPIO_2_5 | GPIO_PAD_CTRL,
+ MX28_PAD_SSP0_DATA6__GPIO_2_6 | GPIO_PAD_CTRL,
+ MX28_PAD_ENET0_RXD2__GPIO_4_9 | GPIO_PAD_CTRL,
/* unused pads */
- MX28_PAD_GPMI_RDY1__GPIO_0_21 | MUX_CONFIG_GPIO,
- MX28_PAD_GPMI_RDY2__GPIO_0_22 | MUX_CONFIG_GPIO,
- MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_GPIO,
- MX28_PAD_GPMI_CE1N__GPIO_0_17 | MUX_CONFIG_GPIO,
- MX28_PAD_GPMI_CE2N__GPIO_0_18 | MUX_CONFIG_GPIO,
- MX28_PAD_GPMI_CE3N__GPIO_0_19 | MUX_CONFIG_GPIO,
+ MX28_PAD_GPMI_RDY1__GPIO_0_21 | GPIO_PAD_CTRL,
+ MX28_PAD_GPMI_RDY2__GPIO_0_22 | GPIO_PAD_CTRL,
+ MX28_PAD_GPMI_RDY3__GPIO_0_23 | GPIO_PAD_CTRL,
+ MX28_PAD_GPMI_CE1N__GPIO_0_17 | GPIO_PAD_CTRL,
+ MX28_PAD_GPMI_CE2N__GPIO_0_18 | GPIO_PAD_CTRL,
+ MX28_PAD_GPMI_CE3N__GPIO_0_19 | GPIO_PAD_CTRL,
- MX28_PAD_SSP0_DATA4__GPIO_2_4 | MUX_CONFIG_GPIO,
- MX28_PAD_SSP0_DATA5__GPIO_2_5 | MUX_CONFIG_GPIO,
- MX28_PAD_SSP0_DATA6__GPIO_2_6 | MUX_CONFIG_GPIO,
- MX28_PAD_SSP0_DATA7__GPIO_2_7 | MUX_CONFIG_GPIO,
-};
+ MX28_PAD_SSP0_DATA4__GPIO_2_4 | GPIO_PAD_CTRL,
+ MX28_PAD_SSP0_DATA7__GPIO_2_7 | GPIO_PAD_CTRL,
+ MX28_PAD_SSP2_SS0__GPIO_2_19 | GPIO_PAD_CTRL,
+ MX28_PAD_SSP2_SS1__GPIO_2_20 | GPIO_PAD_CTRL,
+ MX28_PAD_SSP2_SS2__GPIO_2_21 | GPIO_PAD_CTRL,
+ MX28_PAD_SSP3_SS0__GPIO_2_27 | GPIO_PAD_CTRL,
-static void tx28_stk5_led_on(void)
-{
- gpio_direction_output(MX28_PAD_ENET0_RXD3__GPIO_4_10, 1);
-}
+ MX28_PAD_ENET0_TXD2__GPIO_4_11 | GPIO_PAD_CTRL,
+ MX28_PAD_ENET0_TXD3__GPIO_4_12 | GPIO_PAD_CTRL,
+ MX28_PAD_ENET0_CRS__GPIO_4_15 | GPIO_PAD_CTRL,
+};
-void board_init_ll(void)
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
{
- mx28_common_spl_init(tx28_stk5_pads, ARRAY_SIZE(tx28_stk5_pads));
- tx28_stk5_led_on();
+ mxs_common_spl_init(arg, resptr,
+ tx28_stk5_pads, ARRAY_SIZE(tx28_stk5_pads));
}
-#ifndef CONFIG_TX28_S
static uint32_t tx28_dram_vals[] = {
+#ifdef CONFIG_TX28_S
/* TX28-41x0: NT5TU32M16DG-AC */
/* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
/* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x01010101,
- /* 070 */ 0x000f0f01, 0x0102020a, 0x00000000, 0x00010101,
+ /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x00010101,
+ /* 070 */ 0x000f0f01, 0x0102010a, 0x00000000, 0x00000101,
/* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002,
/* 090 */ 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
/* 0a0 */ 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
/* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004,
/* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000,
/* 2f0 */ 0x00000000, 0x00000000,
-};
-#else
-static uint32_t tx28_dram_vals[] = {
+#elif CONFIG_SYS_SDRAM_SIZE == SZ_128M
/* TX28-40x0: MT47H64M16HR-3 */
/* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
/* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
/* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x00010101,
- /* 070 */ 0x000f0f01, 0x0102010a, 0x00000000, 0x00000101,
+ /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x01010101,
+ /* 070 */ 0x000f0f01, 0x0102020a, 0x00000000, 0x00010101,
/* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002,
/* 090 */ 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8,
/* 0a0 */ 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612,
/* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004,
/* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000,
/* 2f0 */ 0x00000000, 0x00000000,
-};
+#elif CONFIG_SYS_SDRAM_SIZE == SZ_256M
+ /* TX28-40x2: MEM2G16D2DABG */
+ /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 020 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000,
+ /* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x01010101,
+ /* 070 */ 0x000f0f01, 0x0102010a, 0x00000000, 0x00010101,
+ /* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002,
+ /* 090 */ 0x01010000, 0x07080603, 0x07005003, 0x0a0000c8,
+ /* 0a0 */ 0x02009c40, 0x0002030c, 0x00380e09, 0x0328063f,
+ /* 0b0 */ 0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
+ /* 0c0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+ /* 0d0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+ /* 0e0 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ /* 0f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 100 */ 0x00000000, 0x00000000, 0x00000612, 0x01000102,
+ /* 110 */ 0x06120612, 0x00000200, 0x00020007, 0xf4002714,
+ /* 120 */ 0xf4002714, 0xf4002714, 0xf4002714, 0x07400300,
+ /* 130 */ 0x07400300, 0x07400300, 0x07400300, 0x00000005,
+ /* 140 */ 0x00000000, 0x00000000, 0x01000000, 0x01020408,
+ /* 150 */ 0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
+ /* 160 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+ /* 170 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
+ /* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 280 */ 0x00000000, 0x00000000, 0x00010000, 0x00030404,
+ /* 290 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+ /* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x01010000,
+ /* 2b0 */ 0x01000000, 0x03030000, 0x00010303, 0x01020202,
+ /* 2c0 */ 0x00000000, 0x02040303, 0x21002103, 0x00061200,
+ /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004,
+ /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000,
+ /* 2f0 */ 0x00000000, 0x00000000,
+#else
+#error No SDRAM configuration available
#endif
+};
-void mx28_ddr2_setup(void)
+void mxs_adjust_memory_params(uint32_t *dram_vals)
{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(tx28_dram_vals); i++)
- writel(tx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ memcpy(dram_vals, tx28_dram_vals, sizeof(tx28_dram_vals));
}
projects / karo-tx-uboot.git / blobdiff