#include <config.h>
+#include <asm-offsets.h>
#include <configs/tx53.h>
+#include <linux/linkage.h>
#include <asm/arch/imx-regs.h>
#define DEBUG_LED_BIT 20
#define LED_MUX_MODE 0x11
#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
-
-#ifdef PHYS_SDRAM_2_SIZE
-#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-#else
-#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
-#endif
-
+#define SDRAM_SIZE (CONFIG_SYS_SDRAM_SIZE / SZ_1M)
#define REG_CCGR0 0x68
#define REG_CCGR1 0x6c
.error "DCD too large!"
.endif
dcd_end:
+ .section ".pad"
+ .section ".text"
.endm
#define MXC_DCD_CMD_WRT(type, flags) \
#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
#define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)
+#define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100)
.macro CK_VAL, name, clks, offs, max
.iflt \clks - \offs
#define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
/* DDR3 SDRAM */
-#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
-#define BANK_ADDR_BITS 2
-#else
-#define BANK_ADDR_BITS 1
-#endif
+#define BANK_ADDR_BITS CONFIG_NR_DRAM_BANKS
#define SDRAM_BURST_LENGTH 8
#define RALAT 5
#define WALAT 0
#define ADDR_MIRROR 0
#define DDR_TYPE ESDMISC_DDR_TYPE_DDR3
-/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
#if SDRAM_CLK > 666 && SDRAM_CLK <= 800
#define CL_VAL 11
#define CWL_VAL 8
#error SDRAM clock out of range: 303 .. 800
#endif
+#if SDRAM_SIZE < 2048
+/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
+
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
/* ESDCFG0 0x0c */
NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
/* ESDOR 0x30 */
CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#else
+/* 4096MiB SDRAM: IM4G16D3EABG-125I */
+
+#define ROW_ADDR_BITS 15
+#define COL_ADDR_BITS 10
+
+/* ESDCFG0 0x0c */
+NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */
+CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
+CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
+NS_VAL tFAW, 30, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
+
+/* ESDCFG1 0x10 */
+CK_VAL tRCD, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
+CK_VAL tRP, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
+CK_VAL tRC, NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */
+CK_VAL tRAS, NS_TO_CK(35), 1, 31 /* clks - 1 (0..31) */ /* 35 */
+CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
+NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
+
+/* ESDCFG2 0x14 */
+CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
+CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tRRD, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+
+/* ESDOR 0x30 */
+CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#endif
+
#define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)
/* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to
* erroneous Erratum Engcm12377
*/
#define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1)
-
/* ESDOTC 0x08 */
CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
(PWDT << 8) \
)
-#define ROW_ADDR_BITS 14
-#define COL_ADDR_BITS 10
-
#define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
#define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
#define DLL_DISABLE 0
(tODTLon << 12) | \
(tODTLoff << 4))
-fcb_start:
- b _start
- .word 0x20424346 /* "FCB " marker */
- .word 0x01 /* FCB version number */
- .org 0x68
- .word 0x0 /* primary image starting page number */
- .word 0x0 /* secondary image starting page number */
- .word 0x6b
- .word 0x6b
- .word 0x0 /* DBBT start page (0 == NO DBBT) */
- .word 0 /* Bad block marker offset in main area (unused) */
- .org 0xac
- .word 0 /* BI Swap disabled */
- .word 0 /* Bad Block marker offset in spare area */
-fcb_end:
-
- .org 0x400
+ .section ".ivt"
ivt_header:
.word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
app_start_addr:
self_ptr:
.word ivt_header
app_code_csf:
+#ifdef CONFIG_SECURE_BOOT
+ .word __csf_data
+#else
.word 0x0
+#endif
.word 0x0
boot_data:
- .long fcb_start
+ .long CONFIG_SYS_TEXT_BASE
image_len:
- .long CONFIG_U_BOOT_IMG_SIZE
+ .long __uboot_img_len
plugin:
.word 0
ivt_end:
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffcf)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR2, 0x033c0000)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR3, 0x000000ff)
+#ifdef CONFIG_SECURE_BOOT
+ /* enable Sahara */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x0000c000)
+#else
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x00000000)
+#endif
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR5, 0x00fff033)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR6, 0x0f00030f)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR7, 0xfff00000)
MXC_DCD_ITEM(0x53fd4020, 0xb6b12f0a) /* CSCMR2 */
MXC_DCD_ITEM(0x53fd4024, 0x00080b18) /* CSCDR1 */
-#define DDR_SEL_VAL 2
-#define DSE_VAL 5
+#define DDR_SEL_VAL 0
+#define DSE_VAL 6
#define ODT_VAL 2
#define DDR_SEL_SHIFT 25
/* DDR calibration done */
MXC_DCD_ITEM(0x63fd901c, 0x00000000)
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd901c, 0x00004000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
/* setup NFC pads */
/* MUX_SEL */
projects / karo-tx-uboot.git / blobdiff