karo: tx53: fix DDR_SEL value

[karo-tx-uboot.git] / board / karo / tx53 / lowlevel_init.S

diff --git a/board/karo/tx53/lowlevel_init.S b/board/karo/tx53/lowlevel_init.S
index 25d3ddd99ce74efac6b1ab7e6a68d1db341cd19b..ceddce990243ae46f2dc2154ce029b2ec2afbd06 100644 (file)
--- a/board/karo/tx53/lowlevel_init.S
+++ b/board/karo/tx53/lowlevel_init.S
@@ -346,8 +346,7 @@ fcb_start:
        .org    0x68
        .word   0x0     /* primary image starting page number */
        .word   0x0     /* secondary image starting page number */
-       .word   0x6b
-       .word   0x6b
+       .org    0x78
        .word   0x0     /* DBBT start page (0 == NO DBBT) */
        .word   0       /* Bad block marker offset in main area (unused) */
        .org    0xac
@@ -373,7 +372,7 @@ app_code_csf:
 boot_data:
        .long   fcb_start
 image_len:
-       .long   CONFIG_U_BOOT_IMG_SIZE
+       .long   __rel_dyn_end - fcb_start
 plugin:
        .word   0
 ivt_end:
@@ -387,7 +386,7 @@ dcd_hdr:
 
        /* disable all irrelevant clocks */
        MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR0, 0xffcf0fff)
-       MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffc3)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffcf)
        MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR2, 0x033c0000)
        MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR3, 0x000000ff)
        MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x00000000)
@@ -410,7 +409,7 @@ dcd_hdr:
        MXC_DCD_ITEM(0x53fd4020, 0xb6b12f0a)    /* CSCMR2 */
        MXC_DCD_ITEM(0x53fd4024, 0x00080b18)    /* CSCDR1 */
 
-#define DDR_SEL_VAL    2
+#define DDR_SEL_VAL    0
 #define DSE_VAL                5
 #define ODT_VAL                2
 
@@ -516,16 +515,6 @@ dcd_hdr:
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd9040, 0x00010000)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
 
-       /* Write Leveling */
-       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
-       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val | (1 << 7)) | (1 << 9)) /* MRS: start write leveling */
-       MXC_DCD_ITEM(0x63fd901c, 0x00000000)
-       MXC_DCD_ITEM(0x63fd9048, 0x00000001)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001)
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
-       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
-
        /* DQS calibration */
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
@@ -536,7 +525,7 @@ dcd_hdr:
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
 
        /* WR DL calibration */
-       MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+       MXC_DCD_ITEM(0x63fd901c, 0x00008000)
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
        MXC_DCD_ITEM(0x63fd90a4, 0x00000010)