enum LTC3589_REGS {
LTC3589_SCR1 = 0x07,
+ LTC3589_SCR2 = 0x12,
+ LTC3589_VCCR = 0x20,
LTC3589_CLIRQ = 0x21,
LTC3589_B1DTV1 = 0x23,
LTC3589_B1DTV2 = 0x24,
LTC3589_L2DTV2 = 0x33,
};
-#define LTC3589_PGOOD_MASK (1 << 5)
+#define LTC3589_BnDTV1_PGOOD_MASK (1 << 5)
+#define LTC3589_BnDTV1_SLEW(n) (((n) & 3) << 6)
-#define LTC3589_CLK_RATE_LOW (1 << 5)
+#define LTC3589_CLK_RATE_LOW (1 << 5)
+
+#define LTC3589_SCR2_PGOOD_SHUTDWN (1 << 7)
#define VDD_LDO2_VAL mV_to_regval(vout_to_vref(1325 * 10, 2))
-#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1240 * 10, 3))
+#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1100 * 10, 3))
#define VDD_SOC_VAL mV_to_regval(vout_to_vref(1325 * 10, 4))
#define VDD_BUCK3_VAL mV_to_regval(vout_to_vref(2500 * 10, 5))
u8 val;
} ltc3589_regs[] = {
{ LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
+ { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */
- { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_PGOOD_MASK, },
+ { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
{ LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
- { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_PGOOD_MASK, },
+ { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
{ LTC3589_B1DTV2, VDD_CORE_VAL, },
- { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_PGOOD_MASK, },
+ { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
{ LTC3589_B2DTV2, VDD_SOC_VAL, },
- { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_PGOOD_MASK, },
+ { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
{ LTC3589_B3DTV2, VDD_BUCK3_VAL, },
+ /* Select ref 0 for all regulators and enable slew */
+ { LTC3589_VCCR, 0x55, },
+
{ LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
};
return 0;
}
+static struct {
+ u32 max_freq;
+ u32 mV;
+} tx53_core_voltages[] = {
+ { 800000000, 1100, },
+ { 1000000000, 1240, },
+ { 1200000000, 1350, },
+};
+
+int adjust_core_voltage(u32 freq)
+{
+ int ret;
+ int i;
+
+ printf("%s@%d\n", __func__, __LINE__);
+
+ for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) {
+ if (freq <= tx53_core_voltages[i].max_freq) {
+ int retries = 0;
+ const int max_tries = 10;
+ const int delay_us = 1;
+ u32 mV = tx53_core_voltages[i].mV;
+ u8 val = mV_to_regval(vout_to_vref(mV * 10, 3));
+ u8 v;
+
+ printf("regval[%umV]=%02x\n", mV, val);
+
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, LTC3589_B1DTV1, ret);
+ return ret;
+ }
+ printf("Changing reg %02x from %02x to %02x\n",
+ LTC3589_B1DTV1, v, (v & ~0x1f) |
+ mV_to_regval(vout_to_vref(mV * 10, 3)));
+ v &= ~0x1f;
+ v |= mV_to_regval(vout_to_vref(mV * 10, 3));
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC register %02x: %d\n",
+ __func__, LTC3589_B1DTV1, ret);
+ return ret;
+ }
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, LTC3589_VCCR, ret);
+ return ret;
+ }
+ v |= 0x1;
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC register %02x: %d\n",
+ __func__, LTC3589_VCCR, ret);
+ return ret;
+ }
+ for (retries = 0; retries < max_tries; retries++) {
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE,
+ LTC3589_VCCR, 1, &v, 1);
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, LTC3589_VCCR, ret);
+ return ret;
+ }
+ if (!(v & 1))
+ break;
+ udelay(delay_us);
+ }
+ if (v & 1) {
+ printf("change of VDDCORE did not complete after %uµs\n",
+ retries * delay_us);
+ return -ETIMEDOUT;
+ }
+
+ printf("VDDCORE set to %umV after %u loops\n",
+ DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3),
+ 10), retries);
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
int board_early_init_f(void)
{
struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
int ret;
- if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
- break;
-
imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
};
#ifdef CONFIG_LCD
+static u16 tx53_cmap[256];
vidinfo_t panel_info = {
/* set to max. size supported by SoC */
.vl_col = 1600,
.vl_row = 1200,
.vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx53_cmap,
};
static struct fb_videomode tx53_fb_modes[] = {
};
static int lcd_enabled = 1;
+static int lcd_bl_polarity;
+
+static int lcd_backlight_polarity(void)
+{
+ return lcd_bl_polarity;
+}
void lcd_enable(void)
{
udelay(100);
gpio_set_value(TX53_LCD_RST_GPIO, 1);
udelay(300000);
- gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, is_lvds());
+ gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
+ lcd_backlight_polarity());
}
}
{
if (lcd_enabled) {
debug("Switching LCD off\n");
- gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, !is_lvds());
+ gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
+ !lcd_backlight_polarity());
gpio_set_value(TX53_LCD_RST_GPIO, 0);
gpio_set_value(TX53_LCD_PWR_GPIO, 0);
}
struct fb_videomode *p = &tx53_fb_modes[0];
struct fb_videomode fb_mode;
int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
- int pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB24;
+ int pix_fmt;
+ int lcd_bus_width;
ipu_di_clk_parent_t di_clk_parent = is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3;
unsigned long di_clk_rate = 65000000;
}
karo_fdt_move_fdt();
+ lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
if (video_mode == NULL) {
debug("Disabling LCD\n");
imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
ARRAY_SIZE(stk5_lcd_pads));
- debug("Initializing FB driver\n");
-#ifdef CONFIG_SYS_LVDS_IF
- if (pix_fmt == IPU_PIX_FMT_LVDS666) {
- writel(0x01, IOMUXC_BASE_ADDR + 8);
- } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
- writel(0x21, IOMUXC_BASE_ADDR + 8);
+ lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
+ switch (lcd_bus_width) {
+ case 24:
+ pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
+ break;
+
+ case 18:
+ pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
+ break;
+
+ case 16:
+ if (!is_lvds()) {
+ pix_fmt = IPU_PIX_FMT_RGB565;
+ break;
+ }
+ /* fallthru */
+ default:
+ lcd_enabled = 0;
+ printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
+ lcd_bus_width);
+ return;
}
- {
- struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- /* enable LDB & DI0 clock */
- writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
- &ccm_regs->CCGR6);
+ if (is_lvds()) {
+ int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
+ int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
+ uint32_t gpr2;
+
+ if (lvds_chan_mask == 0) {
+ printf("No LVDS channel active\n");
+ lcd_enabled = 0;
+ return;
+ }
+
+ gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
+ if (lcd_bus_width == 24)
+ gpr2 |= (1 << 5) | (1 << 7);
+ gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
+ gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
+ debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
+ writel(gpr2, IOMUXC_BASE_ADDR + 8);
}
-#endif
if (karo_load_splashimage(0) == 0) {
int ret;
static const char *tx53_touchpanels[] = {
"ti,tsc2007",
"edt,edt-ft5x06",
+ "eeti,egalax_ts",
};
void ft_board_setup(void *blob, bd_t *bd)
const char *baseboard = getenv("baseboard");
int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ int ret;
+
+ ret = fdt_increase_size(blob, 4096);
+ if (ret)
+ printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
+
+ if (stk5_v5)
+ karo_fdt_enable_node(blob, "stk5led", 0);
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
fdt_fixup_ethernet(blob);
karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
ARRAY_SIZE(tx53_touchpanels));
- karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
+ karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
karo_fdt_fixup_flexcan(blob, stk5_v5);
tx53_fixup_rtc(blob);
karo_fdt_update_fb_mode(blob, video_mode);
projects / karo-tx-uboot.git / blobdiff