karo: tx6: cleanup DDR calibration code

[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 6953b7b45fd624b9fb00662a7a72987f77ccfd18..7f47eb4d0eca097a224066b3e95ba2caf48abd61 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -411,7 +411,9 @@ ivt_end:
 #define MMDC1_MDRWD                            0x021b002c
 #define MMDC1_MDOR                             0x021b0030
 #define MMDC1_MDASP                            0x021b0040
+
 #define MMDC1_MAPSR                            0x021b0404
+
 #define MMDC1_MPZQHWCTRL                       0x021b0800
 #define MMDC1_MPWLGCR                          0x021b0808
 #define MMDC1_MPWLDECTRL0                      0x021b080c
@@ -444,6 +446,7 @@ ivt_end:
 
 #if PHYS_SDRAM_1_WIDTH == 64
 #define MMDC2_MDPDC                            0x021b4004
+
 #define MMDC2_MPWLGCR                          0x021b4808
 #define MMDC2_MPWLDECTRL0                      0x021b480c
 #define MMDC2_MPWLDECTRL1                      0x021b4810
@@ -855,7 +858,11 @@ dcd_hdr:
 
        /* MDCTL */
        MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
+#if BANK_ADDR_BITS > 1
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (3 << 30))
+#else
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, (1 << 30))
+#endif
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
 
        MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
@@ -888,7 +895,7 @@ dcd_hdr:
 
        /* DDR3 calibration */
        MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
-       MXC_DCD_ITEM(MMDC1_MAPSR,     0x00001007)
+       MXC_DCD_ITEM(MMDC1_MAPSR, 1)
 
        /* ZQ calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
@@ -936,29 +943,24 @@ dcd_hdr:
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
        MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
 
-       MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
 
        MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
        MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
        MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
        MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
+#define MPMUR_FRC_MSR  (1 << 11)
+       MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
 #ifdef DO_DDR_CALIB
-       MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-       MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-       MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000)
+       MXC_DCD_ITEM(MMDC1_MPDGCTRL0, (1 << 30) | (1 << 28) | (0 << 23)) /* choose 32 wait cycles and start DQS calib. */
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_ANY_CLR, MMDC1_MPDGCTRL0, 0x10001000)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
 #else /* DO_DDR_CALIB */
-#define MPMUR_FRC_MSR  (1 << 11)
        MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160)
        MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f)
        MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150)
        MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a)
+       MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
 #endif /* DO_DDR_CALIB */
        MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
        /* DRAM_SDQS[0..7] pad config */
@@ -1008,7 +1010,7 @@ dcd_hdr:
 #endif
        MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
        MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
-       MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006)
+       MXC_DCD_ITEM(MMDC1_MAPSR, (16 << 8))
        MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
 
        /* MDSCR: Normal operation */