karo: tx6: selectively set individual CCGR bits via DCD

[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 02afb607d811cae49b8cf8c21e55aed270043f01..cca946953965285b7f7eddc107e17e38df46983a 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -46,22 +46,22 @@
        .endm
 
 #define MXC_DCD_ITEM(addr, val)                mxc_dcd_item    (addr), (val)
-#if PHYS_SDRAM_1_WIDTH == 16
-#define MXC_DCD_ITEM_16(addr, val)             mxc_dcd_item    (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
+#define MXC_DCD_ITEM_16(addr, val)     mxc_dcd_item    (addr), (val)
 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
 #else
 #define MXC_DCD_ITEM_16(addr, val)
 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
 #endif
-#if PHYS_SDRAM_1_WIDTH > 16
-#define MXC_DCD_ITEM_32(addr, val)             mxc_dcd_item    (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH > 16
+#define MXC_DCD_ITEM_32(addr, val)     mxc_dcd_item    (addr), (val)
 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
 #else
 #define MXC_DCD_ITEM_32(addr, val)
 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
 #endif
-#if PHYS_SDRAM_1_WIDTH == 64
-#define MXC_DCD_ITEM_64(addr, val)             mxc_dcd_item    (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
+#define MXC_DCD_ITEM_64(addr, val)     mxc_dcd_item    (addr), (val)
 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
 #else
 #define MXC_DCD_ITEM_64(addr, val)
@@ -315,7 +315,7 @@ CK_MAX      tCKSRE, NS_TO_CK(10), 5, 0, 7
 #define MDCTL_VAL              (((ROW_ADDR_BITS - 11) << 24) |         \
                                ((COL_ADDR_BITS - 9) << 20) |           \
                                (BURST_LEN << 19) |                     \
-                               ((PHYS_SDRAM_1_WIDTH / 32) << 16) |     \
+                               ((CONFIG_SYS_SDRAM_BUS_WIDTH / 32) << 16) | \
                                ((-1) << (32 - BANK_ADDR_BITS)))
 
 #define MDMISC_WALAT(n)                (((n) & 3) << 16)
@@ -366,7 +366,7 @@ ivt_end:
 #define DCD_VERSION    0x40
 
 #define DDR_SEL_VAL    3 /* DDR3 */
-#if PHYS_SDRAM_1_WIDTH == 16
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
 #define DSE1_VAL       6 /* Drive Strength for DATA lines */
 #define DSE2_VAL       6 /* Drive Strength for ADDR/CMD lines */
 #else
@@ -445,7 +445,7 @@ ivt_end:
 #define MMDC1_MPSWDRDR7                                0x021b08b4
 #define MMDC1_MPMUR0                           0x021b08b8
 
-#if PHYS_SDRAM_1_WIDTH == 64
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
 #define MMDC2_MPWLGCR                          0x021b4808
 #define MMDC2_MPWLDECTRL0                      0x021b480c
 #define MMDC2_MPWLDECTRL1                      0x021b4810
@@ -731,13 +731,16 @@ dcd_hdr:
        MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
 
        /* enable all relevant clocks... */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+#define CCGR(m)                (3 << ((m) * 2))
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* 0xf0c03f3f default: 0xf0c03f0f APBH-DMA */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* 0xf0fc0c00 default: 0xf0fc0000 ENET */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(3)) /* 0xfc3fc0cc default: 0xfc3fc00c I2C1 */
+//     MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR()) /* 0x3ff00000 default: 0x3ff0000f */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* 0xff00ff00 default: 0x0000ff00 GPMI BCH */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(13) | CCGR(12)) /* 0xff033f3f default: 0xf0033f3f UART1 */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(4) | CCGR(3) | CCGR(2) | CCGR(1)) /* 0xffff03ff default: 0xffff0000 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) USDHC1 USDHC1 */
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
        MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
        MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
        MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
@@ -859,7 +862,7 @@ dcd_hdr:
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
 #endif
-#if PHYS_SDRAM_1_WIDTH > 16
+#if CONFIG_SYS_SDRAM_BUS_WIDTH > 16
 #define DO_DDR_CALIB
 #endif
        /* SDRAM initialization */
@@ -995,7 +998,7 @@ dcd_hdr:
        MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
        MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
        MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
-#if PHYS_SDRAM_1_WIDTH == 64
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
 
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */