karo: tx6: replace open coded interpretation of cpurev by calls to is_cpu_type()

[karo-tx-uboot.git] / board / karo / tx6 / lowlevel_init.S

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 3ef04a8f957bb7979b79d938689fdcbb1d4054eb..e8d44801c5fc3d84c3c30f6e14ccd7a5eca60627 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -28,13 +28,14 @@
        (((l) >> 8) & 0x0000FF00) |     \
        (((l) >> 24) & 0x000000FF))
 
-#define CHECK_DCD_ADDR(a)      (                       \
+#define CHECK_DCD_ADDR(a)      (                                       \
        ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ ||        \
-       ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||   \
+       ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ ||           \
        ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ ||        \
-       ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||  \
-       ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
+       ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ ||          \
+       ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ ||         \
        ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ ||     \
+       ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \
        ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
 
        .macro  mxc_dcd_item    addr, val
@@ -434,7 +435,11 @@ ivt_end:
 #define MMDC1_MPWRDLST                         0x021b0854
 #define MMDC1_MPRDDLHWCTL                      0x021b0860
 #define MMDC1_MPWRDLHWCTL                      0x021b0864
+#define MMDC1_MPDGHWST0                                0x021b087c
+#define MMDC1_MPDGHWST1                                0x021b0880
 #define MMDC1_MPPDCMPR2                                0x021b0890
+#define MMDC1_MPDGHWST2                                0x021b0884
+#define MMDC1_MPDGHWST3                                0x021b0888
 #define MMDC1_MPSWDRDR0                                0x021b0898
 #define MMDC1_MPSWDRDR1                                0x021b089c
 #define MMDC1_MPSWDRDR2                                0x021b08a0
@@ -595,9 +600,7 @@ ivt_end:
 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0898
 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e089c
 #define TX6_I2C1_SEL_INP_VAL                   0
-#endif
-
-#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
+#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
 #define IOMUXC_GPR1                            0x020e0004
 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20       0x020e0154
 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21       0x020e0158
@@ -731,13 +734,16 @@ dcd_hdr:
        MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
 
        /* enable all relevant clocks... */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
-       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+#define CCGR(m)                (3 << ((m) * 2))
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* 0xf0c03f3f default: 0xf0c03f0f APBH-DMA */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* 0xf0fc0c00 default: 0xf0fc0000 ENET */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(3)) /* 0xfc3fc0cc default: 0xfc3fc00c I2C1 */
+//     MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR()) /* 0x3ff00000 default: 0x3ff0000f */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* 0xff00ff00 default: 0x0000ff00 GPMI BCH */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(13) | CCGR(12)) /* 0xff033f3f default: 0xf0033f3f UART1 */
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(4) | CCGR(3) | CCGR(2) | CCGR(1)) /* 0xffff03ff default: 0xffff0000 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) USDHC1 USDHC1 */
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
        MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
        MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
        MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
@@ -882,12 +888,22 @@ dcd_hdr:
        MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
        MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
-
-       MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43240334)
-       MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x0324031a)
-       MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x43340344)
-       MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x03280276)
-
+#if defined(CONFIG_SOC_MX6Q)
+       MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43430349)
+       MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x03330334)
+       MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x434b0351)
+       MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x033d030e)
+#elif defined(CONFIG_SOC_MX6DL)
+       MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x423a0236)
+       MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x02210227)
+       MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x42240226)
+       MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x02120223)
+#elif defined(CONFIG_SOC_MX6S)
+       MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x42490244)
+       MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x022f0238)
+#else
+#error No DGCTRL settings for selected SoC
+#endif
        MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
        MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
        MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
@@ -969,8 +985,6 @@ dcd_hdr:
 #if BANK_ADDR_BITS > 1
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
 #endif
-
-       MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
        /* DRAM_SDQS[0..7] pad config */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)