(((l) >> 8) & 0x0000FF00) | \
(((l) >> 24) & 0x000000FF))
-#define CHECK_DCD_ADDR(a) ( \
+#define CHECK_DCD_ADDR(a) ( \
((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
- ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
+ ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
- ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \
- ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
+ ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \
+ ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \
+ ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \
((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
.macro mxc_dcd_item addr, val
.endm
#define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
-#if PHYS_SDRAM_1_WIDTH == 16
-#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
+#define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_16(addr, val)
#define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
#endif
-#if PHYS_SDRAM_1_WIDTH > 16
-#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH > 16
+#define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_32(addr, val)
#define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
#endif
-#if PHYS_SDRAM_1_WIDTH == 64
-#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val)
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
+#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
#else
#define MXC_DCD_ITEM_64(addr, val)
#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
((COL_ADDR_BITS - 9) << 20) | \
(BURST_LEN << 19) | \
- ((PHYS_SDRAM_1_WIDTH / 32) << 16) | \
+ ((CONFIG_SYS_SDRAM_BUS_WIDTH / 32) << 16) | \
((-1) << (32 - BANK_ADDR_BITS)))
#define MDMISC_WALAT(n) (((n) & 3) << 16)
#define DCD_VERSION 0x40
#define DDR_SEL_VAL 3 /* DDR3 */
-#if PHYS_SDRAM_1_WIDTH == 16
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
#define DSE1_VAL 6 /* Drive Strength for DATA lines */
#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
#else
#define MMDC1_MPWRDLST 0x021b0854
#define MMDC1_MPRDDLHWCTL 0x021b0860
#define MMDC1_MPWRDLHWCTL 0x021b0864
+#define MMDC1_MPDGHWST0 0x021b087c
+#define MMDC1_MPDGHWST1 0x021b0880
#define MMDC1_MPPDCMPR2 0x021b0890
+#define MMDC1_MPDGHWST2 0x021b0884
+#define MMDC1_MPDGHWST3 0x021b0888
#define MMDC1_MPSWDRDR0 0x021b0898
#define MMDC1_MPSWDRDR1 0x021b089c
#define MMDC1_MPSWDRDR2 0x021b08a0
#define MMDC1_MPSWDRDR7 0x021b08b4
#define MMDC1_MPMUR0 0x021b08b8
-#if PHYS_SDRAM_1_WIDTH == 64
-#define MMDC2_MDPDC 0x021b4004
-
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
#define MMDC2_MPWLGCR 0x021b4808
#define MMDC2_MPWLDECTRL0 0x021b480c
#define MMDC2_MPWLDECTRL1 0x021b4810
#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898
#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c
#define TX6_I2C1_SEL_INP_VAL 0
-#endif
-
-#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
+#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
#define IOMUXC_GPR1 0x020e0004
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e0154
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158
MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
/* enable all relevant clocks... */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+#define CCGR(m) (3 << ((m) * 2))
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* 0xf0c03f3f default: 0xf0c03f0f APBH-DMA */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* 0xf0fc0c00 default: 0xf0fc0000 ENET */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(3)) /* 0xfc3fc0cc default: 0xfc3fc00c I2C1 */
+// MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR()) /* 0x3ff00000 default: 0x3ff0000f */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* 0xff00ff00 default: 0x0000ff00 GPMI BCH */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(13) | CCGR(12)) /* 0xff033f3f default: 0xf0033f3f UART1 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(4) | CCGR(3) | CCGR(2) | CCGR(1)) /* 0xffff03ff default: 0xffff0000 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) USDHC1 USDHC1 */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
+#endif
+#if CONFIG_SYS_SDRAM_BUS_WIDTH > 16
+#define DO_DDR_CALIB
#endif
/* SDRAM initialization */
+#define WL_DLY_DQS_VAL 30
+#define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS2 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS3 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS4 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS5 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0)
+
+ /* ZQ calibration */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
+ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
+ MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
+
+ MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
+ MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
+ MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
+ MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
+#if defined(CONFIG_SOC_MX6Q)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43430349)
+ MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x03330334)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x434b0351)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x033d030e)
+#elif defined(CONFIG_SOC_MX6DL)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x423a0236)
+ MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x02210227)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x42240226)
+ MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x02120223)
+#elif defined(CONFIG_SOC_MX6S)
+ MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x42490244)
+ MXC_DCD_ITEM_32(MMDC1_MPDGCTRL1, 0x022f0238)
+#else
+#error No DGCTRL settings for selected SoC
+#endif
+ MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
+ MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
+ MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
+ MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
+
/* MPRDDQBY[0..7]DL */
MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
+#define MPMUR_FRC_MSR (1 << 11)
+ MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
+ MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
/* MDMISC */
MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
#endif
-
MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
MXC_DCD_ITEM(MMDC1_MAPSR, 1)
+#ifdef DO_DDR_CALIB
/* ZQ calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-
MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
-
-#define WL_DLY_DQS_VAL 30
-#define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS2 (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS3 (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS4 (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS5 (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0)
- /* Write leveling */
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
- MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_RALAT(~0) | MDMISC_WALAT(~0)) /* increase WALAT/RALAT to max. */
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-
- MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
- MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
- MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
- MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
-
-#if PHYS_SDRAM_1_WIDTH > 16
-#define DO_DDR_CALIB
#endif
- /* DQS gating calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
#if BANK_ADDR_BITS > 1
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
#endif
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
- MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
- MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
-
- MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
-
- MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
- MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
- MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
- MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
-#define MPMUR_FRC_MSR (1 << 11)
- MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
- MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
-#ifdef DO_DDR_CALIB
- MXC_DCD_ITEM(MMDC1_MPDGCTRL0, (1 << 30) | (1 << 28) | (0 << 23)) /* choose 32 wait cycles and start DQS calib. */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_ANY_CLR, MMDC1_MPDGCTRL0, 0x10001000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-#else /* DO_DDR_CALIB */
- MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160)
- MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f)
- MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150)
- MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a)
- MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
- MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
-#endif /* DO_DDR_CALIB */
- MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
/* DRAM_SDQS[0..7] pad config */
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-#else /* DO_DDR_CALIB */
- MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x4a4f4e4c)
- MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x4e50504a)
-#endif /* DO_DDR_CALIB */
-#ifdef DO_DDR_CALIB
+
/* Write delay calibration */
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
-#if PHYS_SDRAM_1_WIDTH == 64
+#if CONFIG_SYS_SDRAM_BUS_WIDTH == 64
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)
#endif
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-#else /* DO_DDR_CALIB */
- MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f)
- MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f)
- MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
- MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
#endif /* DO_DDR_CALIB */
MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
#if BANK_ADDR_BITS > 1
projects / karo-tx-uboot.git / blobdiff