karo: tx6: further cleanups
[karo-tx-uboot.git] / board / karo / tx6 / tx6qdl.c
index 799b25a..06f9fe3 100644 (file)
@@ -1,20 +1,9 @@
 /*
- * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de>
+ * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier:     GPL-2.0+
  *
  */
-
 #include <common.h>
 #include <errno.h>
 #include <libfdt.h>
 #include <asm/gpio.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/hab.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
 
 #include "../common/karo.h"
+#include "pmic.h"
+
+#define __data __attribute__((section(".data")))
 
 #define TX6_FEC_RST_GPIO               IMX_GPIO_NR(7, 6)
 #define TX6_FEC_PWR_GPIO               IMX_GPIO_NR(3, 20)
-#define TX6_FEC_INT_GPIO               IMX_GPIO_NR(2, 4)
+#define TX6_FEC_INT_GPIO               IMX_GPIO_NR(7, 1)
 #define TX6_LED_GPIO                   IMX_GPIO_NR(2, 20)
 
 #define TX6_LCD_PWR_GPIO               IMX_GPIO_NR(2, 31)
 #define TX6_LCD_BACKLIGHT_GPIO         IMX_GPIO_NR(1, 1)
 
 #define TX6_RESET_OUT_GPIO             IMX_GPIO_NR(7, 12)
+#define TX6_I2C1_SCL_GPIO              IMX_GPIO_NR(3, 21)
+#define TX6_I2C1_SDA_GPIO              IMX_GPIO_NR(3, 28)
 
-#define TEMPERATURE_MIN                        -40
+#ifdef CONFIG_MX6_TEMPERATURE_MIN
+#define TEMPERATURE_MIN                        CONFIG_MX6_TEMPERATURE_MIN
+#else
+#define TEMPERATURE_MIN                        (-40)
+#endif
+#ifdef CONFIG_MX6_TEMPERATURE_HOT
+#define TEMPERATURE_HOT                        CONFIG_MX6_TEMPERATURE_HOT
+#else
 #define TEMPERATURE_HOT                        80
-#define TEMPERATURE_MAX                        125
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #define MUX_CFG_SION                   IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
 
-static const iomux_v3_cfg_t tx6qdl_pads[] = {
-       /* NAND flash pads */
-       MX6_PAD_NANDF_CLE__RAWNAND_CLE,
-       MX6_PAD_NANDF_ALE__RAWNAND_ALE,
-       MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
-       MX6_PAD_NANDF_RB0__RAWNAND_READY0,
-       MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
-       MX6_PAD_SD4_CMD__RAWNAND_RDN,
-       MX6_PAD_SD4_CLK__RAWNAND_WRN,
-       MX6_PAD_NANDF_D0__RAWNAND_D0,
-       MX6_PAD_NANDF_D1__RAWNAND_D1,
-       MX6_PAD_NANDF_D2__RAWNAND_D2,
-       MX6_PAD_NANDF_D3__RAWNAND_D3,
-       MX6_PAD_NANDF_D4__RAWNAND_D4,
-       MX6_PAD_NANDF_D5__RAWNAND_D5,
-       MX6_PAD_NANDF_D6__RAWNAND_D6,
-       MX6_PAD_NANDF_D7__RAWNAND_D7,
+char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
+#ifdef CONFIG_SECURE_BOOT
+char __csf_data[0] __attribute__((section(".__csf_data")));
+#endif
 
+static const iomux_v3_cfg_t const tx6qdl_pads[] = {
        /* RESET_OUT */
-       MX6_PAD_GPIO_17__GPIO_7_12,
+       MX6_PAD_GPIO_17__GPIO7_IO12,
 
        /* UART pads */
 #if CONFIG_MXC_UART_BASE == UART1_BASE
-       MX6_PAD_SD3_DAT7__UART1_TXD,
-       MX6_PAD_SD3_DAT6__UART1_RXD,
-       MX6_PAD_SD3_DAT1__UART1_RTS,
-       MX6_PAD_SD3_DAT0__UART1_CTS,
+       MX6_PAD_SD3_DAT7__UART1_TX_DATA,
+       MX6_PAD_SD3_DAT6__UART1_RX_DATA,
+       MX6_PAD_SD3_DAT1__UART1_RTS_B,
+       MX6_PAD_SD3_DAT0__UART1_CTS_B,
 #endif
 #if CONFIG_MXC_UART_BASE == UART2_BASE
-       MX6_PAD_SD4_DAT4__UART2_RXD,
-       MX6_PAD_SD4_DAT7__UART2_TXD,
-       MX6_PAD_SD4_DAT5__UART2_RTS,
-       MX6_PAD_SD4_DAT6__UART2_CTS,
+       MX6_PAD_SD4_DAT4__UART2_RX_DATA,
+       MX6_PAD_SD4_DAT7__UART2_TX_DATA,
+       MX6_PAD_SD4_DAT5__UART2_RTS_B,
+       MX6_PAD_SD4_DAT6__UART2_CTS_B,
 #endif
 #if CONFIG_MXC_UART_BASE == UART3_BASE
-       MX6_PAD_EIM_D24__UART3_TXD,
-       MX6_PAD_EIM_D25__UART3_RXD,
-       MX6_PAD_SD3_RST__UART3_RTS,
-       MX6_PAD_SD3_DAT3__UART3_CTS,
+       MX6_PAD_EIM_D24__UART3_TX_DATA,
+       MX6_PAD_EIM_D25__UART3_RX_DATA,
+       MX6_PAD_SD3_RST__UART3_RTS_B,
+       MX6_PAD_SD3_DAT3__UART3_CTS_B,
 #endif
        /* internal I2C */
        MX6_PAD_EIM_D28__I2C1_SDA,
        MX6_PAD_EIM_D21__I2C1_SCL,
 
        /* FEC PHY GPIO functions */
-       MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
-       MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
-       MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
+       MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
+       MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
+       MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
 };
 
-static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
+static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
        /* FEC functions */
        MX6_PAD_ENET_MDC__ENET_MDC,
        MX6_PAD_ENET_MDIO__ENET_MDIO,
-       MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
+       MX6_PAD_GPIO_16__ENET_REF_CLK,
        MX6_PAD_ENET_RX_ER__ENET_RX_ER,
        MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
-       MX6_PAD_ENET_RXD1__ENET_RDATA_1,
-       MX6_PAD_ENET_RXD0__ENET_RDATA_0,
+       MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
+       MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
        MX6_PAD_ENET_TX_EN__ENET_TX_EN,
-       MX6_PAD_ENET_TXD1__ENET_TDATA_1,
-       MX6_PAD_ENET_TXD0__ENET_TDATA_0,
+       MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
+       MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
 };
 
-static const struct gpio tx6qdl_gpios[] = {
-       { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
-       { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
-       { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
-       { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
+#define TX6_I2C_GPIO_PAD_CTRL  (PAD_CTL_PUS_22K_UP |   \
+                               PAD_CTL_SPEED_MED |     \
+                               PAD_CTL_DSE_34ohm |     \
+                               PAD_CTL_SRE_FAST)
+
+static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
+       /* internal I2C */
+       MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
+       MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
 };
 
-/*
- * Functions
- */
+static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
+       /* internal I2C */
+       MX6_PAD_EIM_D28__I2C1_SDA,
+       MX6_PAD_EIM_D21__I2C1_SCL,
+};
+
+static const struct gpio const tx6qdl_gpios[] = {
+       /* These two entries are used to forcefully reinitialize the I2C bus */
+       { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
+       { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
+
+       { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
+       { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
+       { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
+       { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
+};
+
+static int pmic_addr __data;
+
+#if defined(CONFIG_SOC_MX6Q)
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21       0x020e00a4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28       0x020e00c4
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21       0x020e03b8
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28       0x020e03d8
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0898
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e089c
+#define I2C1_SEL_INPUT_VAL                     0
+#endif
+#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21       0x020e0158
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28       0x020e0174
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21       0x020e0528
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28       0x020e0544
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21     0x020e0868
+#define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28     0x020e086c
+#define I2C1_SEL_INPUT_VAL                     1
+#endif
+
+#define GPIO_DR 0
+#define GPIO_DIR 4
+#define GPIO_PSR 8
+
+static void tx6_i2c_recover(void)
+{
+       int i;
+       int bad = 0;
+#define SCL_BIT                (1 << (TX6_I2C1_SCL_GPIO % 32))
+#define SDA_BIT                (1 << (TX6_I2C1_SDA_GPIO % 32))
+
+       if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
+                       (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
+               return;
+
+       debug("Clearing I2C bus\n");
+       if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
+               printf("I2C SCL stuck LOW\n");
+               bad++;
+
+               writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
+                       GPIO3_BASE_ADDR + GPIO_DR);
+               writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
+                       GPIO3_BASE_ADDR + GPIO_DIR);
+       }
+       if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
+               printf("I2C SDA stuck LOW\n");
+               bad++;
+
+               writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
+                       GPIO3_BASE_ADDR + GPIO_DIR);
+               writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
+                       GPIO3_BASE_ADDR + GPIO_DR);
+               writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
+                       GPIO3_BASE_ADDR + GPIO_DIR);
+
+               imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
+                                               ARRAY_SIZE(tx6_i2c_gpio_pads));
+               udelay(10);
+
+               for (i = 0; i < 18; i++) {
+                       u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
+
+                       debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
+                       writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+                       udelay(10);
+                       if (reg & SCL_BIT &&
+                               readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
+                               break;
+               }
+       }
+       if (bad) {
+               u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
+
+               if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
+                       printf("I2C bus recovery succeeded\n");
+               } else {
+                       printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
+                               SCL_BIT | SDA_BIT);
+               }
+       }
+       debug("Setting up I2C Pads\n");
+       imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
+                                       ARRAY_SIZE(tx6_i2c_pads));
+}
+
 /* placed in section '.data' to prevent overwriting relocation info
  * overlayed with bss
  */
-static u32 wrsr __attribute__((section(".data")));
+static u32 wrsr __data;
 
 #define WRSR_POR                       (1 << 4)
 #define WRSR_TOUT                      (1 << 1)
@@ -192,10 +287,60 @@ static void print_reset_cause(void)
        printf("\n");
 }
 
-int read_cpu_temperature(void);
-int check_cpu_temperature(int boot);
+static const char __data *tx6_mod_suffix;
+
+#ifdef CONFIG_IMX6_THERMAL
+#include <thermal.h>
+#include <imx_thermal.h>
+#include <fuse.h>
 
-static void tx6qdl_print_cpuinfo(void)
+static void print_temperature(void)
+{
+       struct udevice *thermal_dev;
+       int cpu_tmp, minc, maxc, ret;
+       char const *grade_str;
+       static u32 __data thermal_calib;
+
+       puts("Temperature: ");
+       switch (get_cpu_temp_grade(&minc, &maxc)) {
+       case TEMP_AUTOMOTIVE:
+               grade_str = "Automotive";
+               break;
+       case TEMP_INDUSTRIAL:
+               grade_str = "Industrial";
+               break;
+       case TEMP_EXTCOMMERCIAL:
+               grade_str = "Extended Commercial";
+               break;
+       default:
+               grade_str = "Commercial";
+       }
+       printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
+       ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
+       if (ret == 0) {
+               ret = thermal_get_temp(thermal_dev, &cpu_tmp);
+
+               if (ret == 0)
+                       printf(" at %dC", cpu_tmp);
+               else
+                       puts(" - failed to read sensor data");
+       } else {
+               puts(" - no sensor device found");
+       }
+
+       if (fuse_read(1, 6, &thermal_calib) == 0) {
+               printf(" - calibration data 0x%08x\n", thermal_calib);
+       } else {
+               puts(" - Failed to read thermal calib fuse\n");
+       }
+}
+#else
+static inline void print_temperature(void)
+{
+}
+#endif
+
+int checkboard(void)
 {
        u32 cpurev = get_cpu_rev();
        char *cpu_str = "?";
@@ -203,236 +348,172 @@ static void tx6qdl_print_cpuinfo(void)
        switch ((cpurev >> 12) & 0xff) {
        case MXC_CPU_MX6SL:
                cpu_str = "SL";
+               tx6_mod_suffix = "?";
                break;
        case MXC_CPU_MX6DL:
                cpu_str = "DL";
+               tx6_mod_suffix = "U";
                break;
        case MXC_CPU_MX6SOLO:
                cpu_str = "SOLO";
+               tx6_mod_suffix = "S";
                break;
        case MXC_CPU_MX6Q:
                cpu_str = "Q";
+               tx6_mod_suffix = "Q";
                break;
        }
 
-       printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
+       printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
                cpu_str,
                (cpurev & 0x000F0) >> 4,
                (cpurev & 0x0000F) >> 0,
                mxc_get_clock(MXC_ARM_CLK) / 1000000);
 
+       print_temperature();
        print_reset_cause();
+#ifdef CONFIG_MX6_TEMPERATURE_HOT
        check_cpu_temperature(1);
+#endif
+       tx6_i2c_recover();
+       return 0;
+}
+
+/* serial port not initialized at this point */
+int board_early_init_f(void)
+{
+       return 0;
 }
 
-#define LTC3676_BUCK1          0x01
-#define LTC3676_BUCK2          0x02
-#define LTC3676_BUCK3          0x03
-#define LTC3676_BUCK4          0x04
-#define LTC3676_DVB1A          0x0A
-#define LTC3676_DVB1B          0x0B
-#define LTC3676_DVB2A          0x0C
-#define LTC3676_DVB2B          0x0D
-#define LTC3676_DVB3A          0x0E
-#define LTC3676_DVB3B          0x0F
-#define LTC3676_DVB4A          0x10
-#define LTC3676_DVB4B          0x11
-#define LTC3676_MSKPG          0x13
-#define LTC3676_CLIRQ          0x1f
-
-#define LTC3676_BUCK_DVDT_FAST (1 << 0)
-#define LTC3676_BUCK_KEEP_ALIVE        (1 << 1)
-#define LTC3676_BUCK_CLK_RATE_LOW (1 << 2)
-#define LTC3676_BUCK_PHASE_SEL (1 << 3)
-#define LTC3676_BUCK_ENABLE_300        (1 << 4)
-#define LTC3676_BUCK_PULSE_SKIP        (0 << 5)
-#define LTC3676_BUCK_BURST_MODE        (1 << 5)
-#define LTC3676_BUCK_CONTINUOUS        (2 << 5)
-#define LTC3676_BUCK_ENABLE    (1 << 7)
-
-#define LTC3676_PGOOD_MASK     (1 << 5)
-
-#define LTC3676_MSKPG_BUCK1    (1 << 0)
-#define LTC3676_MSKPG_BUCK2    (1 << 1)
-#define LTC3676_MSKPG_BUCK3    (1 << 2)
-#define LTC3676_MSKPG_BUCK4    (1 << 3)
-#define LTC3676_MSKPG_LDO2     (1 << 5)
-#define LTC3676_MSKPG_LDO3     (1 << 6)
-#define LTC3676_MSKPG_LDO4     (1 << 7)
-
-#define VDD_IO_VAL             mV_to_regval(vout_to_vref(3300 * 10, 5))
-#define VDD_IO_VAL_LP          mV_to_regval(vout_to_vref(3100 * 10, 5))
-#define VDD_IO_VAL_2           mV_to_regval(vout_to_vref(3300 * 10, 5_2))
-#define VDD_IO_VAL_2_LP                mV_to_regval(vout_to_vref(3100 * 10, 5_2))
-#define VDD_SOC_VAL            mV_to_regval(vout_to_vref(1425 * 10, 6))
-#define VDD_SOC_VAL_LP         mV_to_regval(vout_to_vref(900 * 10, 6))
-#define VDD_DDR_VAL            mV_to_regval(vout_to_vref(1500 * 10, 7))
-#define VDD_CORE_VAL           mV_to_regval(vout_to_vref(1425 * 10, 8))
-#define VDD_CORE_VAL_LP                mV_to_regval(vout_to_vref(900 * 10, 8))
-
-/* LDO1 */
-#define R1_1                   470
-#define R2_1                   150
-/* LDO4 */
-#define R1_4                   470
-#define R2_4                   150
-/* Buck1 */
-#define R1_5                   390
-#define R2_5                   110
-#define R1_5_2                 470
-#define R2_5_2                 150
-/* Buck2 */
-#define R1_6                   150
-#define R2_6                   180
-/* Buck3 */
-#define R1_7                   150
-#define R2_7                   140
-/* Buck4 */
-#define R1_8                   150
-#define R2_8                   180
-
-/* calculate voltages in 10mV */
-#define R1(idx)                        R1_##idx
-#define R2(idx)                        R2_##idx
-
-#define vout_to_vref(vout, idx)        ((vout) * R2(idx) / (R1(idx) + R2(idx)))
-#define vref_to_vout(vref, idx)        DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
-
-#define mV_to_regval(mV)       DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125)
-#define regval_to_mV(v)                (((v) * 125 + 4125))
-
-static struct ltc3673_regs {
-       u8 addr;
-       u8 val;
-       u8 mask;
-} ltc3676_regs[] = {
-       { LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, },
-       { LTC3676_DVB2B, VDD_SOC_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
-       { LTC3676_DVB3B, VDD_DDR_VAL, ~0x3f, },
-       { LTC3676_DVB4B, VDD_CORE_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
-       { LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, },
-       { LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, },
-       { LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, },
-       { LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
-       { LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, },
-       { LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, },
-       { LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, },
-       { LTC3676_CLIRQ, 0, }, /* clear interrupt status */
+#ifndef CONFIG_MX6_TEMPERATURE_HOT
+static bool tx6_temp_check_enabled = true;
+#else
+#define tx6_temp_check_enabled 0
+#endif
+
+#ifdef CONFIG_TX6_NAND
+#define TX6_FLASH_SZ   (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
+#else
+#ifdef CONFIG_MMC_BOOT_SIZE
+#define TX6_FLASH_SZ   (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
+#else
+#define TX6_FLASH_SZ   2
+#endif
+#endif /* CONFIG_TX6_NAND */
+
+#define TX6_DDR_SZ     (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
+
+static char tx6_mem_table[] = {
+       '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
+       '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
+       '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
+       '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
+       '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
+       '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
+       '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
+       '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
+       '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
+       '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
+       '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
+       '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
 };
 
-static struct ltc3673_regs ltc3676_regs_1[] = {
-       { LTC3676_DVB1B, VDD_IO_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
-       { LTC3676_DVB1A, VDD_IO_VAL, ~0x3f, },
+static struct {
+       uchar addr;
+       uchar rev;
+} tx6_mod_revs[] = {
+       { 0x3c, 1, },
+       { 0x32, 2, },
+       { 0x33, 3, },
 };
 
-static struct ltc3673_regs ltc3676_regs_2[] = {
-       { LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, },
-       { LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, },
+static inline char tx6_mem_suffix(void)
+{
+       size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
+
+       debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
+               TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
+
+       if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
+               return '?';
+
+       return tx6_mem_table[mem_idx];
 };
 
-static int tx6_rev_2(void)
+static int tx6_get_mod_rev(unsigned int pmic_id)
 {
-       struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-       struct fuse_bank5_regs *fuse = (void *)ocotp->bank[5].fuse_regs;
-       u32 pad_settings = readl(&fuse->pad_settings);
+       if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
+               return tx6_mod_revs[pmic_id].rev;
 
-       debug("Fuse pad_settings @ %p = %08x\n",
-               &fuse->pad_settings, pad_settings);
-       return pad_settings & 1;
+       return 0;
 }
 
-static int tx6_ltc3676_setup_regs(struct ltc3673_regs *r, size_t count)
+static int tx6_pmic_probe(void)
 {
-       int ret;
        int i;
 
-       for (i = 0; i < count; i++, r++) {
-#ifdef DEBUG
-               unsigned char value;
+       debug("%s@%d: \n", __func__, __LINE__);
 
-               ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
-               if ((value & ~r->mask) != r->val) {
-                       printf("Changing PMIC reg %02x from %02x to %02x\n",
-                               r->addr, value, r->val);
-               }
-               if (ret) {
-                       printf("%s: failed to read PMIC register %02x: %d\n",
-                               __func__, r->addr, ret);
-                       return ret;
-               }
-#endif
-               ret = i2c_write(CONFIG_SYS_I2C_SLAVE,
-                               r->addr, 1, &r->val, 1);
-               if (ret) {
-                       printf("%s: failed to write PMIC register %02x: %d\n",
-                               __func__, r->addr, ret);
-                       return ret;
+//     i2c_init_all();
+
+       for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
+               u8 i2c_addr = tx6_mod_revs[i].addr;
+               int ret = i2c_probe(i2c_addr);
+
+               if (ret == 0) {
+                       debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
+                       return i;
                }
+               debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
        }
-       return 0;
+       return -EINVAL;
 }
 
-static int setup_pmic_voltages(void)
+int board_init(void)
 {
        int ret;
-       unsigned char value;
+       u32 cpurev = get_cpu_rev();
+       int cpu_variant = (cpurev >> 12) & 0xff;
+       int pmic_id;
 
-       ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
-       if (ret != 0) {
-               printf("Failed to initialize I2C\n");
-               return ret;
-       }
+       debug("%s@%d: \n", __func__, __LINE__);
 
-       ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
-       if (ret) {
-               printf("%s: i2c_read error: %d\n", __func__, ret);
-               return ret;
-       }
+       pmic_id = tx6_pmic_probe();
+       if (pmic_id >= 0)
+               pmic_addr = tx6_mod_revs[pmic_id].addr;
 
-       ret = tx6_ltc3676_setup_regs(ltc3676_regs, ARRAY_SIZE(ltc3676_regs));
-       if (ret)
-               return ret;
+       printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
+               tx6_mod_suffix,
+               cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
+               is_lvds(), tx6_get_mod_rev(pmic_id),
+               tx6_mem_suffix());
 
-       printf("VDDCORE set to %umV\n",
-               DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 8), 10));
-       printf("VDDSOC  set to %umV\n",
-               DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 6), 10));
-
-       if (tx6_rev_2()) {
-               ret = tx6_ltc3676_setup_regs(ltc3676_regs_2,
-                               ARRAY_SIZE(ltc3676_regs_2));
-               printf("VDDIO   set to %umV\n",
-                       DIV_ROUND(vref_to_vout(
-                                       regval_to_mV(VDD_IO_VAL_2), 5_2), 10));
-       } else {
-               ret = tx6_ltc3676_setup_regs(ltc3676_regs_1,
-                               ARRAY_SIZE(ltc3676_regs_1));
-       }
-       return ret;
-}
+       get_hab_status();
 
-int board_early_init_f(void)
-{
-       gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
+       ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
+       if (ret < 0) {
+               printf("Failed to request tx6qdl_gpios: %d\n", ret);
+       }
        imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 
-       return 0;
-}
-
-int board_init(void)
-{
-       int ret;
-
        /* Address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
-#ifdef CONFIG_OF_LIBFDT
        gd->bd->bi_arch_number = -1;
-#else
-       gd->bd->bi_arch_number = 4429;
+
+       if (ctrlc() || (wrsr & WRSR_TOUT)) {
+               if (wrsr & WRSR_TOUT)
+                       printf("WDOG RESET detected; Skipping PMIC setup\n");
+               else
+                       printf("<CTRL-C> detected; safeboot enabled\n");
+#ifndef CONFIG_MX6_TEMPERATURE_HOT
+               tx6_temp_check_enabled = false;
 #endif
-       ret = setup_pmic_voltages();
+               return 0;
+       }
+
+       ret = tx6_pmic_init(pmic_addr);
        if (ret) {
-               printf("Failed to setup PMIC voltages\n");
+               printf("Failed to setup PMIC voltages: %d\n", ret);
                hang();
        }
        return 0;
@@ -440,14 +521,18 @@ int board_init(void)
 
 int dram_init(void)
 {
+       debug("%s@%d: \n", __func__, __LINE__);
+
        /* dram_init must store complete ramsize in gd->ram_size */
        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-                               PHYS_SDRAM_1_SIZE);
+                               PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
        return 0;
 }
 
 void dram_init_banksize(void)
 {
+       debug("%s@%d: \n", __func__, __LINE__);
+
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
                        PHYS_SDRAM_1_SIZE);
@@ -458,29 +543,47 @@ void dram_init_banksize(void)
 #endif
 }
 
-#ifdef CONFIG_CMD_MMC
+#ifdef CONFIG_FSL_ESDHC
+#define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |              \
+       PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
+       PAD_CTL_SRE_FAST)
+
 static const iomux_v3_cfg_t mmc0_pads[] = {
-       MX6_PAD_SD1_CMD__USDHC1_CMD,
-       MX6_PAD_SD1_CLK__USDHC1_CLK,
-       MX6_PAD_SD1_DAT0__USDHC1_DAT0,
-       MX6_PAD_SD1_DAT1__USDHC1_DAT1,
-       MX6_PAD_SD1_DAT2__USDHC1_DAT2,
-       MX6_PAD_SD1_DAT3__USDHC1_DAT3,
+       MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
        /* SD1 CD */
-       MX6_PAD_SD3_CMD__GPIO_7_2,
+       MX6_PAD_SD3_CMD__GPIO7_IO02,
 };
 
 static const iomux_v3_cfg_t mmc1_pads[] = {
-       MX6_PAD_SD2_CMD__USDHC2_CMD,
-       MX6_PAD_SD2_CLK__USDHC2_CLK,
-       MX6_PAD_SD2_DAT0__USDHC2_DAT0,
-       MX6_PAD_SD2_DAT1__USDHC2_DAT1,
-       MX6_PAD_SD2_DAT2__USDHC2_DAT2,
-       MX6_PAD_SD2_DAT3__USDHC2_DAT3,
+       MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
        /* SD2 CD */
-       MX6_PAD_SD3_CLK__GPIO_7_3,
+       MX6_PAD_SD3_CLK__GPIO7_IO03,
 };
 
+#ifdef CONFIG_TX6_EMMC
+static const iomux_v3_cfg_t mmc3_pads[] = {
+       MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
+       /* eMMC RESET */
+       MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
+                                               PAD_CTL_DSE_40ohm),
+};
+#endif
+
 static struct tx6_esdhc_cfg {
        const iomux_v3_cfg_t *pads;
        int num_pads;
@@ -488,6 +591,18 @@ static struct tx6_esdhc_cfg {
        struct fsl_esdhc_cfg cfg;
        int cd_gpio;
 } tx6qdl_esdhc_cfg[] = {
+#ifdef CONFIG_TX6_EMMC
+       {
+               .pads = mmc3_pads,
+               .num_pads = ARRAY_SIZE(mmc3_pads),
+               .clkid = MXC_ESDHC4_CLK,
+               .cfg = {
+                       .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
+                       .max_bus_width = 4,
+               },
+               .cd_gpio = -EINVAL,
+       },
+#endif
        {
                .pads = mmc0_pads,
                .num_pads = ARRAY_SIZE(mmc0_pads),
@@ -512,9 +627,7 @@ static struct tx6_esdhc_cfg {
 
 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 {
-       void *p = cfg;
-
-       return p - offsetof(struct tx6_esdhc_cfg, cfg);
+       return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 }
 
 int board_mmc_getcd(struct mmc *mmc)
@@ -522,11 +635,12 @@ int board_mmc_getcd(struct mmc *mmc)
        struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 
        if (cfg->cd_gpio < 0)
-               return cfg->cd_gpio;
+               return 1;
 
-       debug("SD card %d is %spresent\n",
+       debug("SD card %d is %spresent (GPIO %d)\n",
                cfg - tx6qdl_esdhc_cfg,
-               gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
+               gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
+               cfg->cd_gpio);
        return !gpio_get_value(cfg->cd_gpio);
 }
 
@@ -534,23 +648,24 @@ int board_mmc_init(bd_t *bis)
 {
        int i;
 
+       debug("%s@%d: \n", __func__, __LINE__);
+
        for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
                struct mmc *mmc;
                struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
                int ret;
 
-               if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
-                       break;
-
                cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
                imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 
-               ret = gpio_request_one(cfg->cd_gpio,
-                               GPIOF_INPUT, "MMC CD");
-               if (ret) {
-                       printf("Error %d requesting GPIO%d_%d\n",
-                               ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
-                       continue;
+               if (cfg->cd_gpio >= 0) {
+                       ret = gpio_request_one(cfg->cd_gpio,
+                                       GPIOFLAG_INPUT, "MMC CD");
+                       if (ret) {
+                               printf("Error %d requesting GPIO%d_%d\n",
+                                       ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
+                               continue;
+                       }
                }
 
                debug("%s: Initializing MMC slot %d\n", __func__, i);
@@ -559,7 +674,7 @@ int board_mmc_init(bd_t *bis)
                mmc = find_mmc_device(i);
                if (mmc == NULL)
                        continue;
-               if (board_mmc_getcd(mmc) > 0)
+               if (board_mmc_getcd(mmc))
                        mmc_init(mmc);
        }
        return 0;
@@ -568,11 +683,6 @@ int board_mmc_init(bd_t *bis)
 
 #ifdef CONFIG_FEC_MXC
 
-#define FEC_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
-                       PAD_CTL_SRE_FAST)
-#define FEC_PAD_CTL2   (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
-#define GPIO_PAD_CTL   (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
-
 #ifndef ETH_ALEN
 #define ETH_ALEN 6
 #endif
@@ -581,10 +691,13 @@ int board_eth_init(bd_t *bis)
 {
        int ret;
 
+       debug("%s@%d: \n", __func__, __LINE__);
+
        /* delay at least 21ms for the PHY internal POR signal to deassert */
        udelay(22000);
 
-       imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
+       imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
+                                       ARRAY_SIZE(tx6qdl_fec_pads));
 
        /* Deassert RESET to the external phy */
        gpio_set_value(TX6_FEC_RST_GPIO, 1);
@@ -595,6 +708,24 @@ int board_eth_init(bd_t *bis)
 
        return ret;
 }
+
+static void tx6_init_mac(void)
+{
+       u8 mac[ETH_ALEN];
+
+       imx_get_mac_from_fuse(0, mac);
+       if (!is_valid_ethaddr(mac)) {
+               printf("No valid MAC address programmed\n");
+               return;
+       }
+
+       printf("MAC addr from fuse: %pM\n", mac);
+       eth_setenv_enetaddr("ethaddr", mac);
+}
+#else
+static inline void tx6_init_mac(void)
+{
+}
 #endif /* CONFIG_FEC_MXC */
 
 enum {
@@ -603,10 +734,13 @@ enum {
        LED_STATE_ON,
 };
 
-static inline int calc_blink_rate(int tmp)
+static inline int calc_blink_rate(void)
 {
+       if (!tx6_temp_check_enabled)
+               return CONFIG_SYS_HZ;
+
        return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
-               (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
+               (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
                (TEMPERATURE_HOT - TEMPERATURE_MIN);
 }
 
@@ -620,10 +754,10 @@ void show_activity(int arg)
                last = get_timer(0);
                gpio_set_value(TX6_LED_GPIO, 1);
                led_state = LED_STATE_ON;
-               blink_rate = calc_blink_rate(check_cpu_temperature(0));
+               blink_rate = calc_blink_rate();
        } else {
                if (get_timer(last) > blink_rate) {
-                       blink_rate = calc_blink_rate(check_cpu_temperature(0));
+                       blink_rate = calc_blink_rate();
                        last = get_timer_masked();
                        if (led_state == LED_STATE_ON) {
                                gpio_set_value(TX6_LED_GPIO, 0);
@@ -637,79 +771,52 @@ void show_activity(int arg)
 
 static const iomux_v3_cfg_t stk5_pads[] = {
        /* SW controlled LED on STK5 baseboard */
-       MX6_PAD_EIM_A18__GPIO_2_20,
-
-       /* LCD data pins */
-       MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
-       MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
-       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
-       MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
-       MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
-       MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
-       MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
-       MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
-       MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
-       MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
-       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
-       MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
-       MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
-       MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
-       MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
-       MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
-       MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
-       MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
-       MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
-       MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
-       MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
-       MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
-       MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
-       MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
-       MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
-       MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
-       MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
-       MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
+       MX6_PAD_EIM_A18__GPIO2_IO20,
 
        /* I2C bus on DIMM pins 40/41 */
        MX6_PAD_GPIO_6__I2C3_SDA,
        MX6_PAD_GPIO_3__I2C3_SCL,
 
        /* TSC200x PEN IRQ */
-       MX6_PAD_EIM_D26__GPIO_3_26,
+       MX6_PAD_EIM_D26__GPIO3_IO26,
 
        /* EDT-FT5x06 Polytouch panel */
-       MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
-       MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
-       MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
+       MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
+       MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
+       MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
 
        /* USBH1 */
-       MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
-       MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
+       MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
+       MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
        /* USBOTG */
-       MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
-       MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
-       MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
+       MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
+       MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
+       MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
 };
 
 static const struct gpio stk5_gpios[] = {
-       { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
+       { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 
-       { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
-       { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
-       { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
-       { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
-       { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
+       { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
+       { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
+       { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
+       { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
+       { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 };
 
 #ifdef CONFIG_LCD
+static u16 tx6_cmap[256];
 vidinfo_t panel_info = {
        /* set to max. size supported by SoC */
        .vl_col = 1920,
        .vl_row = 1080,
 
-       .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+       .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+       .cmap = tx6_cmap,
 };
 
 static struct fb_videomode tx6_fb_modes[] = {
+#ifndef CONFIG_SYS_LVDS_IF
        {
                /* Standard VGA timing */
                .name           = "VGA",
@@ -775,7 +882,6 @@ static struct fb_videomode tx6_fb_modes[] = {
                .upper_margin   = 2,
                .vsync_len      = 10,
                .lower_margin   = 2,
-               .sync           = FB_SYNC_CLK_LAT_FALL,
        },
        {
                /* Emerging ET0500G0DH6 800 x 480 display.
@@ -828,6 +934,42 @@ static struct fb_videomode tx6_fb_modes[] = {
                .lower_margin   = 525 - 480 - 35,
                .sync           = FB_SYNC_CLK_LAT_FALL,
        },
+       {
+               /* Emerging ET070001DM6 800 x 480 display.
+                * 152.4 mm x 91.44 mm display area.
+                */
+               .name           = "ET070001DM6",
+               .refresh        = 60,
+               .xres           = 800,
+               .yres           = 480,
+               .pixclock       = KHZ2PICOS(33260),
+               .left_margin    = 216 - 128,
+               .hsync_len      = 128,
+               .right_margin   = 1056 - 800 - 216,
+               .upper_margin   = 35 - 2,
+               .vsync_len      = 2,
+               .lower_margin   = 525 - 480 - 35,
+               .sync           = 0,
+       },
+#else
+       {
+               /* HannStar HSD100PXN1
+                * 202.7m mm x 152.06 mm display area.
+                */
+               .name           = "HSD100PXN1",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 768,
+               .pixclock       = KHZ2PICOS(65000),
+               .left_margin    = 0,
+               .hsync_len      = 0,
+               .right_margin   = 320,
+               .upper_margin   = 0,
+               .vsync_len      = 0,
+               .lower_margin   = 38,
+               .sync           = FB_SYNC_CLK_LAT_FALL,
+       },
+#endif
        {
                /* unnamed entry for assigning parameters parsed from 'video_mode' string */
                .refresh        = 60,
@@ -842,6 +984,12 @@ static struct fb_videomode tx6_fb_modes[] = {
 };
 
 static int lcd_enabled = 1;
+static int lcd_bl_polarity;
+
+static int lcd_backlight_polarity(void)
+{
+       return lcd_bl_polarity;
+}
 
 void lcd_enable(void)
 {
@@ -852,15 +1000,16 @@ void lcd_enable(void)
         */
        lcd_is_enabled = 0;
 
-       karo_load_splashimage(1);
-
        if (lcd_enabled) {
+               karo_load_splashimage(1);
+
                debug("Switching LCD on\n");
                gpio_set_value(TX6_LCD_PWR_GPIO, 1);
                udelay(100);
                gpio_set_value(TX6_LCD_RST_GPIO, 1);
                udelay(300000);
-               gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
+               gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
+                       lcd_backlight_polarity());
        }
 }
 
@@ -876,7 +1025,8 @@ void lcd_panel_disable(void)
 {
        if (lcd_enabled) {
                debug("Switching LCD off\n");
-               gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 1);
+               gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
+                       !lcd_backlight_polarity());
                gpio_set_value(TX6_LCD_RST_GPIO, 0);
                gpio_set_value(TX6_LCD_PWR_GPIO, 0);
        }
@@ -884,61 +1034,63 @@ void lcd_panel_disable(void)
 
 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
        /* LCD RESET */
-       MX6_PAD_EIM_D29__GPIO_3_29,
+       MX6_PAD_EIM_D29__GPIO3_IO29,
        /* LCD POWER_ENABLE */
-       MX6_PAD_EIM_EB3__GPIO_2_31,
+       MX6_PAD_EIM_EB3__GPIO2_IO31,
        /* LCD Backlight (PWM) */
-       MX6_PAD_GPIO_1__GPIO_1_1,
+       MX6_PAD_GPIO_1__GPIO1_IO01,
 
+#ifndef CONFIG_SYS_LVDS_IF
        /* Display */
-       MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
-       MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
-       MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
-       MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
-       MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
-       MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
-       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
-       MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
-       MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
-       MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
-       MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
-       MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
-       MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
-       MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
-       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
-       MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
-       MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
-       MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
-       MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
-       MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
-       MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
-       MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
-       MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
-       MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
-       MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
-       MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
-       MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
-       MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+       MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+       MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+       MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+       MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+       MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+       MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+       MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+       MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+       MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+       MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+       MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+       MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+       MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+       MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+       MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+       MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+       MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
+       MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
+       MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
+       MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
+       MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
+       MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
+       MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
+       MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
+       MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
+       MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
+#endif
 };
 
 static const struct gpio stk5_lcd_gpios[] = {
-       { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
-       { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
-       { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
+       { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
+       { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
+       { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 };
 
 void lcd_ctrl_init(void *lcdbase)
 {
        int color_depth = 24;
-       const char *video_mode = getenv("video_mode");
+       const char *video_mode = karo_get_vmode(getenv("video_mode"));
        const char *vm;
        unsigned long val;
        int refresh = 60;
        struct fb_videomode *p = &tx6_fb_modes[0];
        struct fb_videomode fb_mode;
        int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
-       int pix_fmt = 0;
-       ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
+       int pix_fmt;
+       int lcd_bus_width;
        unsigned long di_clk_rate = 65000000;
 
        if (!lcd_enabled) {
@@ -946,7 +1098,7 @@ void lcd_ctrl_init(void *lcdbase)
                return;
        }
 
-       if (tstc() || (wrsr & WRSR_TOUT)) {
+       if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
                debug("Disabling LCD\n");
                lcd_enabled = 0;
                setenv("splashimage", NULL);
@@ -954,15 +1106,15 @@ void lcd_ctrl_init(void *lcdbase)
        }
 
        karo_fdt_move_fdt();
+       lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 
-       vm = karo_fdt_set_display(video_mode, "", "/soc/aips-bus/ldb");
-       if (vm == NULL) {
+       if (video_mode == NULL) {
                debug("Disabling LCD\n");
                lcd_enabled = 0;
                return;
        }
-       video_mode = vm;
-       if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
+       vm = video_mode;
+       if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
                p = &fb_mode;
                debug("Using video mode from FDT\n");
                vm += strlen(vm);
@@ -1009,7 +1161,7 @@ void lcd_ctrl_init(void *lcdbase)
                                        switch (val) {
                                        case 32:
                                        case 24:
-                                               if (pix_fmt == IPU_PIX_FMT_LVDS666)
+                                               if (is_lvds())
                                                        pix_fmt = IPU_PIX_FMT_LVDS888;
                                                /* fallthru */
                                        case 16:
@@ -1018,7 +1170,7 @@ void lcd_ctrl_init(void *lcdbase)
                                                break;
 
                                        case 18:
-                                               if (pix_fmt == IPU_PIX_FMT_LVDS666) {
+                                               if (is_lvds()) {
                                                        color_depth = val;
                                                        break;
                                                }
@@ -1051,19 +1203,6 @@ void lcd_ctrl_init(void *lcdbase)
                        break;
 
                default:
-                       if (!pix_fmt) {
-                               char *tmp;
-
-                               if (strncmp(vm, "LVDS", 4) == 0) {
-                                       pix_fmt = IPU_PIX_FMT_LVDS666;
-                                       di_clk_parent = DI_PCLK_LDB;
-                               } else {
-                                       pix_fmt = IPU_PIX_FMT_RGB24;
-                               }
-                               tmp = strchr(vm, ':');
-                               if (tmp)
-                                       vm = tmp;
-                       }
                        if (*vm != '\0')
                                vm++;
                }
@@ -1095,16 +1234,15 @@ void lcd_ctrl_init(void *lcdbase)
                panel_info.vl_bpix = LCD_COLOR16;
                break;
        default:
-               panel_info.vl_bpix = LCD_COLOR24;
+               panel_info.vl_bpix = LCD_COLOR32;
        }
 
        p->pixclock = KHZ2PICOS(refresh *
                (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
-               (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
-               / 1000);
+               (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
+                               1000);
        debug("Pixel clock set to %lu.%03lu MHz\n",
-               PICOS2KHZ(p->pixclock) / 1000,
-               PICOS2KHZ(p->pixclock) % 1000);
+               PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 
        if (p != &fb_mode) {
                int ret;
@@ -1121,25 +1259,63 @@ void lcd_ctrl_init(void *lcdbase)
        imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
                                        ARRAY_SIZE(stk5_lcd_pads));
 
-       debug("Initializing FB driver\n");
-       if (!pix_fmt)
-               pix_fmt = IPU_PIX_FMT_RGB24;
-       else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
-               writel(0x01, IOMUXC_BASE_ADDR + 8);
-       } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
-               writel(0x21, IOMUXC_BASE_ADDR + 8);
-       }
-       if (pix_fmt != IPU_PIX_FMT_RGB24) {
-               struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-               /* enable LDB & DI0 clock */
-               writel(readl(&ccm_regs->CCGR3) | MXC_CCM_CCGR3_LDB_DI0_MASK |
-                       MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK,
-                       &ccm_regs->CCGR3);
+       lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
+       switch (lcd_bus_width) {
+       case 24:
+               pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
+               break;
+
+       case 18:
+               pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
+               break;
+
+       case 16:
+               if (!is_lvds()) {
+                       pix_fmt = IPU_PIX_FMT_RGB565;
+                       break;
+               }
+               /* fallthru */
+       default:
+               lcd_enabled = 0;
+               printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
+                       lcd_bus_width);
+               return;
        }
+       if (is_lvds()) {
+               int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
+               int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
+               uint32_t gpr2;
+               uint32_t gpr3;
+
+               if (lvds_chan_mask == 0) {
+                       printf("No LVDS channel active\n");
+                       lcd_enabled = 0;
+                       return;
+               }
 
+               gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
+               if (lcd_bus_width == 24)
+                       gpr2 |= (1 << 5) | (1 << 7);
+               gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
+               gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
+               debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
+               writel(gpr2, IOMUXC_BASE_ADDR + 8);
+
+               gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
+               gpr3 &= ~((3 << 8) | (3 << 6));
+               writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
+       }
        if (karo_load_splashimage(0) == 0) {
+               int ret;
+
                debug("Initializing LCD controller\n");
-               ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
+               ret = ipuv3_fb_init(p, 0, pix_fmt,
+                               is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
+                               di_clk_rate, -1);
+               if (ret) {
+                       printf("Failed to initialize FB driver: %d\n", ret);
+                       lcd_enabled = 0;
+               }
        } else {
                debug("Skipping initialization of LCD controller\n");
        }
@@ -1150,7 +1326,13 @@ void lcd_ctrl_init(void *lcdbase)
 
 static void stk5_board_init(void)
 {
-       gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+       int ret;
+
+       ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
+       if (ret < 0) {
+               printf("Failed to request stk5_gpios: %d\n", ret);
+               return;
+       }
        imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 }
 
@@ -1161,53 +1343,68 @@ static void stk5v3_board_init(void)
 
 static void stk5v5_board_init(void)
 {
+       int ret;
+
        stk5_board_init();
 
-       gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
+       ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
                        "Flexcan Transceiver");
-       imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
+       if (ret) {
+               printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
+               return;
+       }
+
+       imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
 }
 
 static void tx6qdl_set_cpu_clock(void)
 {
        unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 
-       if (tstc() || (wrsr & WRSR_TOUT))
-               return;
-
        if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
                return;
 
+       if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
+               printf("%s detected; skipping cpu clock change\n",
+                       (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
+               return;
+       }
        if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
                cpu_clk = mxc_get_clock(MXC_ARM_CLK);
                printf("CPU clock set to %lu.%03lu MHz\n",
                        cpu_clk / 1000000, cpu_clk / 1000 % 1000);
        } else {
-               printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
+               printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
        }
 }
 
-static void tx6_init_mac(void)
-{
-       u8 mac[ETH_ALEN];
-
-       imx_get_mac_from_fuse(-1, mac);
-       if (!is_valid_ether_addr(mac)) {
-               printf("No valid MAC address programmed\n");
-               return;
-       }
-
-       eth_setenv_enetaddr("ethaddr", mac);
-       printf("MAC addr from fuse: %pM\n", mac);
-}
-
 int board_late_init(void)
 {
        int ret = 0;
        const char *baseboard;
+#if 1
+       /* override secure_boot fuse */
+       struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+       struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
+
+       writel(0x12, &fuse->cfg5);
+#endif
+
+       debug("%s@%d: \n", __func__, __LINE__);
+
+       env_cleanup();
+
+       if (tx6_temp_check_enabled)
+               check_cpu_temperature(1);
 
        tx6qdl_set_cpu_clock();
-       karo_fdt_move_fdt();
+
+       if (had_ctrlc())
+               setenv_ulong("safeboot", 1);
+       else if (wrsr & WRSR_TOUT)
+               setenv_ulong("wdreset", 1);
+       else
+               karo_fdt_move_fdt();
 
        baseboard = getenv("baseboard");
        if (!baseboard)
@@ -1242,24 +1439,10 @@ exit:
        tx6_init_mac();
 
        gpio_set_value(TX6_RESET_OUT_GPIO, 1);
+       clear_ctrlc();
        return ret;
 }
 
-int checkboard(void)
-{
-       u32 cpurev = get_cpu_rev();
-       int cpu_variant = (cpurev >> 12) & 0xff;
-
-       tx6qdl_print_cpuinfo();
-
-       printf("Board: Ka-Ro TX6%c-%dx1%d\n",
-               cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
-               cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
-               1 - PHYS_SDRAM_1_WIDTH / 64);
-
-       return 0;
-}
-
 #ifdef CONFIG_SERIAL_TAG
 void get_board_serial(struct tag_serialnr *serialnr)
 {
@@ -1275,30 +1458,44 @@ void get_board_serial(struct tag_serialnr *serialnr)
 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 #include <jffs2/jffs2.h>
 #include <mtd_node.h>
-struct node_info nodes[] = {
+static struct node_info nodes[] = {
        { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
 };
-
 #else
 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
 #endif
 
-void ft_board_setup(void *blob, bd_t *bd)
+static const char *tx6_touchpanels[] = {
+       "ti,tsc2007",
+       "edt,edt-ft5x06",
+       "eeti,egalax_ts",
+};
+
+int ft_board_setup(void *blob, bd_t *bd)
 {
        const char *baseboard = getenv("baseboard");
        int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
-       const char *video_mode = getenv("video_mode");
+       const char *video_mode = karo_get_vmode(getenv("video_mode"));
+       int ret;
 
-       karo_fdt_enable_node(blob, "stk5led", !stk5_v5);
+       ret = fdt_increase_size(blob, 4096);
+       if (ret) {
+               printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
+               return ret;
+       }
+       if (stk5_v5)
+               karo_fdt_enable_node(blob, "stk5led", 0);
 
        fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
        fdt_fixup_ethernet(blob);
 
-       karo_fdt_fixup_touchpanel(blob);
-       karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
+       karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
+                               ARRAY_SIZE(tx6_touchpanels));
+       karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
        karo_fdt_fixup_flexcan(blob, stk5_v5);
 
-       video_mode = karo_fdt_set_display(video_mode, "", "/soc/aips-bus/ldb");
        karo_fdt_update_fb_mode(blob, video_mode);
+
+       return 0;
 }
 #endif /* CONFIG_OF_BOARD_SETUP */