#define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
static const iomux_v3_cfg_t tx6qdl_pads[] = {
+#ifndef CONFIG_NO_NAND
/* NAND flash pads */
MX6_PAD_NANDF_CLE__RAWNAND_CLE,
MX6_PAD_NANDF_ALE__RAWNAND_ALE,
MX6_PAD_NANDF_D5__RAWNAND_D5,
MX6_PAD_NANDF_D6__RAWNAND_D6,
MX6_PAD_NANDF_D7__RAWNAND_D7,
-
+#endif
/* RESET_OUT */
MX6_PAD_GPIO_17__GPIO_7_12,
int read_cpu_temperature(void);
int check_cpu_temperature(int boot);
+static const char *tx6_mod_suffix;
+
static void tx6qdl_print_cpuinfo(void)
{
u32 cpurev = get_cpu_rev();
switch ((cpurev >> 12) & 0xff) {
case MXC_CPU_MX6SL:
cpu_str = "SL";
+ tx6_mod_suffix = "?";
break;
case MXC_CPU_MX6DL:
cpu_str = "DL";
+ tx6_mod_suffix = "U";
break;
case MXC_CPU_MX6SOLO:
cpu_str = "SOLO";
+ tx6_mod_suffix = "S";
break;
case MXC_CPU_MX6Q:
cpu_str = "Q";
+ tx6_mod_suffix = "Q";
break;
}
}
#ifdef CONFIG_CMD_MMC
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
static const iomux_v3_cfg_t mmc0_pads[] = {
- MX6_PAD_SD1_CMD__USDHC1_CMD,
- MX6_PAD_SD1_CLK__USDHC1_CLK,
- MX6_PAD_SD1_DAT0__USDHC1_DAT0,
- MX6_PAD_SD1_DAT1__USDHC1_DAT1,
- MX6_PAD_SD1_DAT2__USDHC1_DAT2,
- MX6_PAD_SD1_DAT3__USDHC1_DAT3,
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* SD1 CD */
MX6_PAD_SD3_CMD__GPIO_7_2,
};
static const iomux_v3_cfg_t mmc1_pads[] = {
- MX6_PAD_SD2_CMD__USDHC2_CMD,
- MX6_PAD_SD2_CLK__USDHC2_CLK,
- MX6_PAD_SD2_DAT0__USDHC2_DAT0,
- MX6_PAD_SD2_DAT1__USDHC2_DAT1,
- MX6_PAD_SD2_DAT2__USDHC2_DAT2,
- MX6_PAD_SD2_DAT3__USDHC2_DAT3,
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* SD2 CD */
MX6_PAD_SD3_CLK__GPIO_7_3,
};
+#ifdef CONFIG_MMC_BOOT_SIZE
+static const iomux_v3_cfg_t mmc3_pads[] = {
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* eMMC RESET */
+ MX6_PAD_NANDF_ALE__USDHC4_RST,
+};
+#endif
+
static struct tx6_esdhc_cfg {
const iomux_v3_cfg_t *pads;
int num_pads;
struct fsl_esdhc_cfg cfg;
int cd_gpio;
} tx6qdl_esdhc_cfg[] = {
+#ifdef CONFIG_MMC_BOOT_SIZE
+ {
+ .pads = mmc3_pads,
+ .num_pads = ARRAY_SIZE(mmc3_pads),
+ .clkid = MXC_ESDHC4_CLK,
+ .cfg = {
+ .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
+ .max_bus_width = 4,
+ },
+ .cd_gpio = -EINVAL,
+ },
+#endif
{
.pads = mmc0_pads,
.num_pads = ARRAY_SIZE(mmc0_pads),
struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
if (cfg->cd_gpio < 0)
- return cfg->cd_gpio;
+ return 1;
debug("SD card %d is %spresent\n",
cfg - tx6qdl_esdhc_cfg,
cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
- ret = gpio_request_one(cfg->cd_gpio,
- GPIOF_INPUT, "MMC CD");
- if (ret) {
- printf("Error %d requesting GPIO%d_%d\n",
- ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
- continue;
+ if (cfg->cd_gpio >= 0) {
+ ret = gpio_request_one(cfg->cd_gpio,
+ GPIOF_INPUT, "MMC CD");
+ if (ret) {
+ printf("Error %d requesting GPIO%d_%d\n",
+ ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
+ continue;
+ }
}
debug("%s: Initializing MMC slot %d\n", __func__, i);
mmc = find_mmc_device(i);
if (mmc == NULL)
continue;
- if (board_mmc_getcd(mmc) > 0)
+ if (board_mmc_getcd(mmc))
mmc_init(mmc);
}
return 0;
return ret;
}
+#ifdef CONFIG_NO_NAND
+#ifdef CONFIG_MMC_BOOT_SIZE
+#define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 1024 - 1 + 2)
+#else
+#define TX6_FLASH_SZ 3
+#endif
+#else /* CONFIG_NO_NAND */
+#define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
+#endif /* CONFIG_NO_NAND */
+
+#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
+#define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
+#else
+#define TX6_DDR_SZ 2
+#endif
+
+#if CONFIG_TX6_REV >= 0x3
+static char tx6_mem_table[] = {
+ '4', /* 256MiB SDRAM; 128MiB NAND */
+ '1', /* 512MiB SDRAM; 128MiB NAND */
+ '0', /* 1GiB SDRAM; 128MiB NAND */
+ '?', /* 256MiB SDRAM; 256MiB NAND */
+ '?', /* 512MiB SDRAM; 256MiB NAND */
+ '2', /* 1GiB SDRAM; 256MiB NAND */
+ '?', /* 256MiB SDRAM; 4GiB eMMC */
+ '5', /* 512MiB SDRAM; 4GiB eMMC */
+ '3', /* 1GiB SDRAM; 4GiB eMMC */
+ '?', /* 256MiB SDRAM; 8GiB eMMC */
+ '?', /* 512MiB SDRAM; 8GiB eMMC */
+ '?', /* 1GiB SDRAM; 8GiB eMMC */
+};
+
+static inline char tx6_mem_suffix(void)
+{
+ size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
+
+ debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
+ TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
+
+ if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
+ return '?';
+
+ return tx6_mem_table[mem_idx];
+};
+#else /* CONFIG_TX6_REV >= 0x3 */
+static inline char tx6_mem_suffix(void)
+{
+#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH
+ if (CONFIG_SYS_SDRAM_BUS_WIDTH == 32)
+ return '1';
+#endif
+#ifdef CONFIG_SYS_NAND_BLOCKS
+ if (CONFIG_SYS_NAND_BLOCKS == 2048)
+ return '2';
+#endif
+ return '0';
+}
+#endif /* CONFIG_TX6_REV >= 0x3 */
+
int checkboard(void)
{
u32 cpurev = get_cpu_rev();
tx6qdl_print_cpuinfo();
- printf("Board: Ka-Ro TX6%c-%d%d1%d\n",
- cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
+ printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
+ tx6_mod_suffix,
cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
- is_lvds(), 1 - PHYS_SDRAM_1_WIDTH / 64 +
- 2 * (CONFIG_SYS_NAND_BLOCKS / 1024 - 1));
+ is_lvds(), CONFIG_TX6_REV,
+ tx6_mem_suffix());
return 0;
}