karo: tx6: disable gpmi clk before changing podf and clk_sel

[karo-tx-uboot.git] / board / karo / tx6 / tx6ul_ll_init.S

diff --git a/board/karo/tx6/tx6ul_ll_init.S b/board/karo/tx6/tx6ul_ll_init.S
index 299e469d7b70e8ba810cce98c43003262602d6eb..bdd2214c9a4dceee5c515d85e5fed02dab5fec92 100644 (file)
--- a/board/karo/tx6/tx6ul_ll_init.S
+++ b/board/karo/tx6/tx6ul_ll_init.S
@@ -22,6 +22,8 @@
 #define SDRAM_SIZE             PHYS_SDRAM_1_SIZE
 #endif
 
+#define CCGR(m)                        (3 << ((m) * 2))
+
 #define CPU_2_BE_32(l)                 \
        ((((l) << 24) & 0xFF000000) |   \
        (((l) << 8) & 0x00FF0000) |     \
@@ -559,11 +561,22 @@ dcd_hdr:
        /* ETN PHY Power */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5, 0x00000015)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5, 0x000010b0)
+#ifndef CONFIG_TX6_EMMC
+       /* switch NFC clock to 99MHz */
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
        MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x000336c1 */
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
+       MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+#endif
        MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
 
        MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002005) /* ENET PLL */
-#define CCGR(m)                (3 << ((m) * 2))
+
        /* enable all relevant clocks... */
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
        /* enable UART clock depending on selected console port */