MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
+#if defined(KM_PCIE_RESET_MPP7)
+ MPP7_GPO,
+#else
MPP7_PEX_RST_OUTn,
+#endif
#if defined(CONFIG_SYS_I2C_SOFT)
MPP8_GPIO, /* SDA */
MPP9_GPIO, /* SCL */
/*
* Wait for startup OK from mgcoge3ne
*/
-int startup_allowed(void)
+static int startup_allowed(void)
{
unsigned char buf;
return 0;
}
-#if defined(CONFIG_BOOTCOUNT_LIMIT)
static void set_bootcount_addr(void)
{
uchar buf[32];
sprintf((char *)buf, "0x%x", bootcountaddr);
setenv("bootcountaddr", (char *)buf);
}
-#endif
int misc_init_r(void)
{
initialize_unit_leds();
set_km_env();
-#if defined(CONFIG_BOOTCOUNT_LIMIT)
set_bootcount_addr();
-#endif
return 0;
}
return;
/* RGMII clk transition on data stable */
- if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
+ if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
printf("Error reading PHY spec ctrl reg\n");
- if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
- reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
+ if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+ reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
printf("Error writing PHY spec ctrl reg\n");
/* leds setup */
- if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
- PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
+ if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+ PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
printf("Error writing PHY LED reg\n");
/* reset the phy */
#if defined(CONFIG_KM_NUSA)
struct mv88e_sw_reg extsw_conf[] = {
/*
- * port 0, PIGGY4, autoneg
+ * port 0, PIGGY4, autoneg
* first the fix for the 1000Mbits Autoneg, this is from
* a Marvell errata, the regs are undocumented
*/