fsl: Clean up printing of PCI boot info

[karo-tx-uboot.git] / board / pm856 / pm856.c

diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c
index bfde6959b4eceee7cea35941bf5829eea5e887fe..4e059b08594fd038b545f184ac134af378110cc0 100644 (file)
--- a/board/pm856/pm856.c
+++ b/board/pm856/pm856.c
@@ -28,17 +28,18 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
+#include <netdev.h>
 
 #if defined(CONFIG_DDR_ECC)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-extern long int spd_sdram(void);
-
 void local_bus_init(void);
 long int fixed_sdram(void);
 
@@ -212,10 +213,10 @@ int checkboard (void)
        puts("Board: MicroSys PM856\n");
 
 #ifdef CONFIG_PCI
-       printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+       printf("PCI1: 32 bit, %d MHz (compiled)\n",
               CONFIG_SYS_CLK_FREQ / 1000000);
 #else
-       printf("    PCI1: disabled\n");
+       printf("PCI1: disabled\n");
 #endif
 
        /*
@@ -227,17 +228,17 @@ int checkboard (void)
 }
 
 
-long int
+phys_size_t
 initdram(int board_type)
 {
        long dram_size = 0;
-       extern long spd_sdram (void);
+
 
        puts("Initializing\n");
 
 #if defined(CONFIG_DDR_DLL)
        {
-           volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+           volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
            int i,x;
 
            x = 10;
@@ -250,7 +251,7 @@ initdram(int board_type)
            udelay (200);
            while (gur->ddrdllcr != 0x81000100)
            {
-               gur->devdisr = gur->devdisr | 0x00010000;
+               gur->devdisr = gur->devdisr | 0x00010000;
                asm("sync;isync;msync");
                for (i=0; i<x; i++)
                    ;
@@ -262,7 +263,9 @@ initdram(int board_type)
 #endif
 
 #if defined(CONFIG_SPD_EEPROM)
-       dram_size = spd_sdram ();
+       dram_size = fsl_ddr_sdram();
+       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+       dram_size *= 0x100000;
 #else
        dram_size = fixed_sdram ();
 #endif
@@ -286,8 +289,8 @@ initdram(int board_type)
 void
 local_bus_init(void)
 {
-       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-       volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
        uint clkdiv;
        uint lbc_hz;
@@ -297,20 +300,20 @@ local_bus_init(void)
         * Errata LBC11.
         * Fix Local Bus clock glitch when DLL is enabled.
         *
-        * If localbus freq is < 66Mhz, DLL bypass mode must be used.
-        * If localbus freq is > 133Mhz, DLL can be safely enabled.
+        * If localbus freq is < 66MHz, DLL bypass mode must be used.
+        * If localbus freq is > 133MHz, DLL can be safely enabled.
         * Between 66 and 133, the DLL is enabled with an override workaround.
         */
 
        get_sys_info(&sysinfo);
-       clkdiv = lbc->lcrr & 0x0f;
+       clkdiv = lbc->lcrr & LCRR_CLKDIV;
        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
        if (lbc_hz < 66) {
-               lbc->lcrr = CFG_LBC_LCRR | 0x80000000;  /* DLL Bypass */
+               lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;   /* DLL Bypass */
 
        } else if (lbc_hz >= 133) {
-               lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+               lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 
        } else {
                /*
@@ -325,7 +328,7 @@ local_bus_init(void)
                        lbc->lcrr = 0x10000004;
                }
 
-               lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+               lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
                udelay(200);
 
                /*
@@ -338,11 +341,11 @@ local_bus_init(void)
        }
 }
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-       uint *pstart = (uint *) CFG_MEMTEST_START;
-       uint *pend = (uint *) CFG_MEMTEST_END;
+       uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+       uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
        uint *p;
 
        printf("SDRAM test phase 1:\n");
@@ -379,15 +382,15 @@ int testdram (void)
  ************************************************************************/
 long int fixed_sdram (void)
 {
-  #ifndef CFG_RAMBOOT
-       volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
-
-       ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-       ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-       ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-       ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-       ddr->sdram_mode = CFG_DDR_MODE;
-       ddr->sdram_interval = CFG_DDR_INTERVAL;
+  #ifndef CONFIG_SYS_RAMBOOT
+       volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+
+       ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+       ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+       ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+       ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+       ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+       ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
     #if defined (CONFIG_DDR_ECC)
        ddr->err_disable = 0x0000000D;
        ddr->err_sbe = 0x00ff0000;
@@ -396,14 +399,14 @@ long int fixed_sdram (void)
        udelay(500);
     #if defined (CONFIG_DDR_ECC)
        /* Enable ECC checking */
-       ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+       ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
     #else
-       ddr->sdram_cfg = CFG_DDR_CONTROL;
+       ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
     #endif
        asm("sync; isync; msync");
        udelay(500);
   #endif
-       return CFG_SDRAM_SIZE * 1024 * 1024;
+       return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif /* !defined(CONFIG_SPD_EEPROM) */
 
@@ -442,3 +445,9 @@ pci_init_board(void)
        pci_mpc85xx_init(&hose);
 #endif /* CONFIG_PCI */
 }
+
+int board_eth_init(bd_t *bis)
+{
+       cpu_eth_init(bis);      /* Intialize TSECs first */
+       return pci_eth_init(bis);
+}