rename CFG_ macros to CONFIG_SYS

[karo-tx-uboot.git] / board / purple / purple.c

diff --git a/board/purple/purple.c b/board/purple/purple.c
index 900e66f72f8a2ee70526ef0b14160812d47fd1b4..54bef651ced1c34ff9375d2f8813fb0494474f8d 100644 (file)
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -129,14 +129,14 @@ phys_size_t initdram(int board_type)
 {
        /* The only supported number of SDRAM banks is 4.
         */
-#define CFG_NB 4
+#define CONFIG_SYS_NB  4
 
        ulong   cfgpb0  = *INCA_IP_SDRAM_MC_CFGPB0;
        ulong   cfgdw   = *INCA_IP_SDRAM_MC_CFGDW;
        int     cols    = cfgpb0 & 0xF;
        int     rows    = (cfgpb0 & 0xF0) >> 4;
        int     dw      = cfgdw & 0xF;
-       ulong   size    = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
+       ulong   size    = (1 << (rows + cols)) * (1 << (dw - 1)) * CONFIG_SYS_NB;
        void (*  sdram_init) (ulong);
 
        sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
@@ -253,26 +253,26 @@ void copy_code (ulong dest_addr)
 
        /* copy u-boot code
         */
-       copyLongs((ulong *)CFG_MONITOR_BASE,
+       copyLongs((ulong *)CONFIG_SYS_MONITOR_BASE,
                  (ulong *)dest_addr,
-                 ((ulong)&uboot_end_data - CFG_MONITOR_BASE + 3) / 4);
+                 ((ulong)&uboot_end_data - CONFIG_SYS_MONITOR_BASE + 3) / 4);
 
 
        /* flush caches
         */
 
        start = CKSEG0;
-       end = start + CFG_DCACHE_SIZE;
+       end = start + CONFIG_SYS_DCACHE_SIZE;
        while(start < end) {
                cache_unroll(start,Index_Writeback_Inv_D);
-               start += CFG_CACHELINE_SIZE;
+               start += CONFIG_SYS_CACHELINE_SIZE;
        }
 
        start = CKSEG0;
-       end = start + CFG_ICACHE_SIZE;
+       end = start + CONFIG_SYS_ICACHE_SIZE;
        while(start < end) {
                cache_unroll(start,Index_Invalidate_I);
-               start += CFG_CACHELINE_SIZE;
+               start += CONFIG_SYS_CACHELINE_SIZE;
        }
 }