imported Freescale specific U-Boot additions for i.MX28,... release L2.6.31_10.08.01

[karo-tx-uboot.git] / board / purple / purple.c

diff --git a/board/purple/purple.c b/board/purple/purple.c
index 4c3e5b44b5303ed161d30fe90a885658e5755f2d..54bef651ced1c34ff9375d2f8813fb0494474f8d 100755 (executable)
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -23,33 +23,43 @@
 
 #include <common.h>
 #include <command.h>
+#include <netdev.h>
 #include <asm/inca-ip.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>
+#include <asm/io.h>
 #include <asm/addrspace.h>
 #include <asm/cacheops.h>
+#include <asm/reboot.h>
 
 #include "sconsole.h"
 
-#define cache_unroll(base,op)                  \
-       __asm__ __volatile__("                  \
-               .set noreorder;                 \
-               .set mips3;                     \
-               cache %1, (%0);                 \
-               .set mips0;                     \
-               .set reorder"                   \
-               :                               \
-               : "r" (base),                   \
+#define cache_unroll(base,op)          \
+       __asm__ __volatile__("          \
+               .set noreorder;         \
+               .set mips3;             \
+               cache %1, (%0);         \
+               .set mips0;             \
+               .set reorder"           \
+               :                       \
+               : "r" (base),           \
                  "i" (op));
 
 typedef void (*FUNCPTR)(ulong *source, ulong *destination, ulong nlongs);
 
 extern void    asc_serial_init         (void);
-extern void    asc_serial_putc         (char);
-extern void    asc_serial_puts         (const char *);
-extern int     asc_serial_getc         (void);
-extern int     asc_serial_tstc         (void);
-extern void    asc_serial_setbrg       (void);
+extern void    asc_serial_putc         (char);
+extern void    asc_serial_puts         (const char *);
+extern int     asc_serial_getc         (void);
+extern int     asc_serial_tstc         (void);
+extern void    asc_serial_setbrg       (void);
+
+void _machine_restart(void)
+{
+       void (*f)(void) = (void *) 0xbfc00000;
+
+       f();
+}
 
 static void sdram_timing_init (ulong size)
 {
@@ -76,16 +86,16 @@ static void sdram_timing_init (ulong size)
                        while (p4 < 32 && done == 0) {
                            WRITE_MC_IOGP_1;
 
-                           for (addr = KSEG1 + 0x4000;
-                                addr < KSEG1ADDR (size);
+                           for (addr = CKSEG1 + 0x4000;
+                                addr < CKSEG1ADDR (size);
                                 addr = addr + 4) {
                                        *(uint *) addr = 0xaa55aa55;
                            }
 
                            pass = 1;
 
-                           for (addr = KSEG1 + 0x4000;
-                                addr < KSEG1ADDR (size) && pass == 1;
+                           for (addr = CKSEG1 + 0x4000;
+                                addr < CKSEG1ADDR (size) && pass == 1;
                                 addr = addr + 4) {
                                        if (*(uint *) addr != 0xaa55aa55)
                                                pass = 0;
@@ -115,21 +125,21 @@ static void sdram_timing_init (ulong size)
        }
 }
 
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
        /* The only supported number of SDRAM banks is 4.
         */
-#define CFG_NB 4
+#define CONFIG_SYS_NB  4
 
        ulong   cfgpb0  = *INCA_IP_SDRAM_MC_CFGPB0;
        ulong   cfgdw   = *INCA_IP_SDRAM_MC_CFGDW;
        int     cols    = cfgpb0 & 0xF;
        int     rows    = (cfgpb0 & 0xF0) >> 4;
        int     dw      = cfgdw & 0xF;
-       ulong   size    = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
+       ulong   size    = (1 << (rows + cols)) * (1 << (dw - 1)) * CONFIG_SYS_NB;
        void (*  sdram_init) (ulong);
 
-       sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init);
+       sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
 
        sdram_init(0x10000);
 
@@ -145,6 +155,8 @@ int checkboard (void)
 
        printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000);
 
+       set_io_port_base(0);
+
        return 0;
 }
 
@@ -173,8 +185,7 @@ static void copydwords (ulong *source, ulong *destination, ulong nlongs)
        ulong temp,temp1;
        ulong *dstend = destination + nlongs;
 
-       while (destination < dstend)
-       {
+       while (destination < dstend) {
                temp = *source++;
                /* dummy read from sdram */
                temp1 = *(ulong *)0xa0000000;
@@ -242,25 +253,32 @@ void copy_code (ulong dest_addr)
 
        /* copy u-boot code
         */
-       copyLongs((ulong *)CFG_MONITOR_BASE,
+       copyLongs((ulong *)CONFIG_SYS_MONITOR_BASE,
                  (ulong *)dest_addr,
-                 ((ulong)&uboot_end_data - CFG_MONITOR_BASE + 3) / 4);
+                 ((ulong)&uboot_end_data - CONFIG_SYS_MONITOR_BASE + 3) / 4);
 
 
        /* flush caches
         */
 
-       start = KSEG0;
-       end = start + CFG_DCACHE_SIZE;
+       start = CKSEG0;
+       end = start + CONFIG_SYS_DCACHE_SIZE;
        while(start < end) {
                cache_unroll(start,Index_Writeback_Inv_D);
-               start += CFG_CACHELINE_SIZE;
+               start += CONFIG_SYS_CACHELINE_SIZE;
        }
 
-       start = KSEG0;
-       end = start + CFG_ICACHE_SIZE;
+       start = CKSEG0;
+       end = start + CONFIG_SYS_ICACHE_SIZE;
        while(start < end) {
                cache_unroll(start,Index_Invalidate_I);
-               start += CFG_CACHELINE_SIZE;
+               start += CONFIG_SYS_CACHELINE_SIZE;
        }
 }
+
+#ifdef CONFIG_PLB2800_ETHER
+int board_eth_init(bd_t *bis)
+{
+       return plb2800_eth_initialize(bis);
+}
+#endif