Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / board / samsung / smdk5250 / clock_init.c

diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c
index c009ae579a313aecce41ed09bc6f0e599f1d80ea..b288e66f0ebef945c91fe1d5db8b426b77f5394c 100644 (file)
--- a/board/samsung/smdk5250/clock_init.c
+++ b/board/samsung/smdk5250/clock_init.c
@@ -28,10 +28,14 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/spl.h>
+#include <asm/arch/dwmmc.h>
 
 #include "clock_init.h"
 #include "setup.h"
 
+#define FSYS1_MMC0_DIV_MASK    0xff0f
+#define FSYS1_MMC0_DIV_VAL     0x0701
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct arm_clk_ratios arm_clk_ratios[] = {
@@ -434,10 +438,10 @@ void system_clock_init()
                val = readl(&clk->mux_stat_core1);
        } while ((val | MUX_MPLL_SEL_MASK) != val);
 
-       clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK);
-       clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK);
-       clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK);
-       clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK);
+       clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
+       clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
+       clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
+       clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
        tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
                | MUX_GPLL_SEL_MASK;
        do {
@@ -494,35 +498,35 @@ void system_clock_init()
        val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
                        arm_clk_ratio->apll_sdiv);
        writel(val, &clk->apll_con0);
-       while (readl(&clk->apll_con0) & APLL_CON0_LOCKED)
+       while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
                ;
 
        /* Set MPLL */
        writel(MPLL_CON1_VAL, &clk->mpll_con1);
        val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
        writel(val, &clk->mpll_con0);
-       while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED)
+       while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
                ;
 
        /* Set BPLL */
        writel(BPLL_CON1_VAL, &clk->bpll_con1);
        val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
        writel(val, &clk->bpll_con0);
-       while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED)
+       while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
                ;
 
        /* Set CPLL */
        writel(CPLL_CON1_VAL, &clk->cpll_con1);
        val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
        writel(val, &clk->cpll_con0);
-       while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED)
+       while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
                ;
 
        /* Set GPLL */
        writel(GPLL_CON1_VAL, &clk->gpll_con1);
        val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
        writel(val, &clk->gpll_con0);
-       while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED)
+       while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
                ;
 
        /* Set EPLL */
@@ -530,7 +534,7 @@ void system_clock_init()
        writel(EPLL_CON1_VAL, &clk->epll_con1);
        val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
        writel(val, &clk->epll_con0);
-       while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED)
+       while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
                ;
 
        /* Set VPLL */
@@ -538,7 +542,7 @@ void system_clock_init()
        writel(VPLL_CON1_VAL, &clk->vpll_con1);
        val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
        writel(val, &clk->vpll_con0);
-       while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED)
+       while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
                ;
 
        writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
@@ -664,3 +668,17 @@ void clock_init_dp_clock(void)
        /* We run DP at 267 Mhz */
        setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
 }
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
+ */
+void emmc_boot_clk_div_set(void)
+{
+       struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+       unsigned int div_mmc;
+
+       div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
+       div_mmc |= FSYS1_MMC0_DIV_VAL;
+       writel(div_mmc, (unsigned int) &clk->div_fsys1);
+}