*/
-extern long int spd_sdram (void);
-
#include <common.h>
#include <asm/processor.h>
+#include <asm/mmu.h>
#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
#include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
long int fixed_sdram (void);
int board_early_init_f (void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
pci->peer &= 0xfffffffdf; /* disable master abort */
#endif
void reset_phy (void)
{
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
- volatile unsigned char *bcsr = (unsigned char *) CFG_BCSR;
+ volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR;
#endif
/* reset Giga bit Ethernet port if needed here */
int checkboard (void)
{
sys_info_t sysinfo;
+ char buf[32];
get_sys_info (&sysinfo);
#else
printf ("Board: Wind River SBC8540 Board\n");
#endif
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
- printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
- if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
- || (CFG_LBC_LCRR & 0x0f) == 8) {
- printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+ printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
+ printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
+ printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
+ if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
+ || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
+ printf ("\tLBC: %s MHz\n",
+ strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));
} else {
printf("\tLBC: unknown\n");
}
- printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+ printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
return (0);
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long dram_size = 0;
- extern long spd_sdram (void);
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
#if 0
#if !defined(CONFIG_RAM_AS_FLASH)
- volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#endif /* 0 */
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
- volatile ccsr_gur_t *gur= &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;
#endif
#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram ();
+ dram_size = fsl_ddr_sdram();
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#else
dram_size = fixed_sdram ();
#endif
#if 0
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
get_sys_info(&sysinfo);
- /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
- if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
- lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+ /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
+ if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
+ lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
#endif
- lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
udelay(200);
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
- lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
- lbc->br2 = CFG_BR2_PRELIM;
- lbc->lbcr = CFG_LBC_LBCR;
- lbc->lsdmr = CFG_LBC_LSDMR_1;
+ lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
+ lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CFG_LBC_LSDMR_2;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CFG_LBC_LSDMR_3;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CFG_LBC_LSDMR_4;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CFG_LBC_LSDMR_5;
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
asm("sync");
- lbc->lsrt = CFG_LBC_LSRT;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
asm("sync");
- lbc->mrtpr = CFG_LBC_MRTPR;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("sync");
#endif
#endif
{
/* Initialize all of memory for ECC, then
* enable errors */
- uint *p = 0;
- uint i = 0;
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
- dma_init();
- for (*p = 0; p < (uint *)(8 * 1024); p++) {
- if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
- *p = (unsigned int)0xdeadbeef;
- if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
- }
+ volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- /* 8K */
- dma_xfer((uint *)0x2000,0x2000,(uint *)0);
- /* 16K */
- dma_xfer((uint *)0x4000,0x4000,(uint *)0);
- /* 32K */
- dma_xfer((uint *)0x8000,0x8000,(uint *)0);
- /* 64K */
- dma_xfer((uint *)0x10000,0x10000,(uint *)0);
- /* 128k */
- dma_xfer((uint *)0x20000,0x20000,(uint *)0);
- /* 256k */
- dma_xfer((uint *)0x40000,0x40000,(uint *)0);
- /* 512k */
- dma_xfer((uint *)0x80000,0x80000,(uint *)0);
- /* 1M */
- dma_xfer((uint *)0x100000,0x100000,(uint *)0);
- /* 2M */
- dma_xfer((uint *)0x200000,0x200000,(uint *)0);
- /* 4M */
- dma_xfer((uint *)0x400000,0x400000,(uint *)0);
-
- for (i = 1; i < dram_size / 0x800000; i++) {
- dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
- }
+ dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
/* Enable errors for ECC */
ddr->err_disable = 0x00000000;
}
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
long int fixed_sdram (void)
{
-#define CFG_DDR_CONTROL 0xc2000000
+#define CONFIG_SYS_DDR_CONTROL 0xc2000000
- #ifndef CFG_RAMBOOT
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ #ifndef CONFIG_SYS_RAMBOOT
+ volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+#if (CONFIG_SYS_SDRAM_SIZE == 512)
+ ddr->cs0_bnds = 0x0000000f;
+#else
ddr->cs0_bnds = 0x00000007;
+#endif
ddr->cs1_bnds = 0x0010001f;
ddr->cs2_bnds = 0x00000000;
ddr->cs3_bnds = 0x00000000;
udelay(500);
#if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */
- ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
- ddr->sdram_cfg = CFG_DDR_CONTROL;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
#endif
asm("sync; isync; msync");
udelay(500);
#endif
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+#ifdef CONFIG_PCI
+ const char *path;
+#endif
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose.last_busno - hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
projects / karo-tx-uboot.git / blobdiff