imported Freescale specific U-Boot additions for i.MX28,... release L2.6.31_10.08.01

[karo-tx-uboot.git] / board / sc520_cdp / sc520_cdp.c

diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c
index b6add59bb482dd14363eea6f3030c325854bdb1b..830ec37dd76f01e949ddd7b99e131b27a35f119a 100755 (executable)
--- a/board/sc520_cdp/sc520_cdp.c
+++ b/board/sc520_cdp/sc520_cdp.c
@@ -27,8 +27,9 @@
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/ic/sc520.h>
-#include <asm/ic/ali512x.h>
+#include <ali512x.h>
 #include <spi.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -86,7 +87,7 @@ static void irq_init(void)
        write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
        write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
 
-       if (CFG_USE_SIO_UART) {
+       if (CONFIG_SYS_USE_SIO_UART) {
                write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
                write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
                write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3);          /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
@@ -113,7 +114,7 @@ static void irq_init(void)
 
 }
 
-
+#ifdef CONFIG_PCI
 /* PCI stuff */
 static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 {
@@ -121,14 +122,14 @@ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
         * when we need one (a board with more pci interrupt pins
         * would use a larger table */
        static int irq_list[] = {
-               CFG_FIRST_PCI_IRQ,
-               CFG_SECOND_PCI_IRQ,
-               CFG_THIRD_PCI_IRQ,
-               CFG_FORTH_PCI_IRQ
+               CONFIG_SYS_FIRST_PCI_IRQ,
+               CONFIG_SYS_SECOND_PCI_IRQ,
+               CONFIG_SYS_THIRD_PCI_IRQ,
+               CONFIG_SYS_FORTH_PCI_IRQ
        };
        static int next_irq_index=0;
 
-       char tmp_pin;
+       uchar tmp_pin;
        int pin;
 
        pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
@@ -192,7 +193,7 @@ void pci_init_board(void)
 {
        pci_sc520_init(&sc520_cdp_hose);
 }
-
+#endif
 
 static void silence_uart(int port)
 {
@@ -233,9 +234,9 @@ static void bus_init(void)
 {
 
        /* set up the GP IO pins */
-       write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff);     /* set the GPIO pin function 31-16 reg */
-       write_mmcr_word(SC520_PIOPFS15_0, 0xffff);      /* set the GPIO pin function 15-0 reg */
-       write_mmcr_byte(SC520_CSPFS, 0xf8);             /* set the CS pin function  reg */
+       write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff);     /* set the GPIO pin function 31-16 reg */
+       write_mmcr_word(SC520_PIOPFS15_0, 0xffff);      /* set the GPIO pin function 15-0 reg */
+       write_mmcr_byte(SC520_CSPFS, 0xf8);             /* set the CS pin function  reg */
        write_mmcr_byte(SC520_CLKSEL, 0x70);
 
 
@@ -278,7 +279,7 @@ static void bus_init(void)
 
        asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
 
-       if (CFG_USE_SIO_UART) {
+       if (CONFIG_SYS_USE_SIO_UART) {
                write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
                setup_ali_sio(1);
        } else {
@@ -507,6 +508,7 @@ int dram_init(void)
 
 void show_boot_progress(int val)
 {
+       if (val < -32) val = -1;  /* let things compatible */
        outb(val&0xff, 0x80);
        outb((val&0xff00)>>8, 0x680);
 }
@@ -561,22 +563,22 @@ void spi_eeprom_probe(int x)
 {
 }
 
-int spi_eeprom_read(int x, int offset, char *buffer, int len)
+int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
 {
        return 0;
 }
 
-int spi_eeprom_write(int x, int offset, char *buffer, int len)
+int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
 {
        return 0;
 }
 
 void spi_init_f(void)
 {
-#ifdef CONFIG_SC520_CDP_USE_SPI
+#ifdef CONFIG_SYS_SC520_CDP_USE_SPI
        spi_eeprom_probe(1);
 #endif
-#ifdef CONFIG_SC520_CDP_USE_MW
+#ifdef CONFIG_SYS_SC520_CDP_USE_MW
        mw_eeprom_probe(2);
 #endif
 }
@@ -593,13 +595,13 @@ ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
                offset |= addr[i];
        }
 
-#ifdef CONFIG_SC520_CDP_USE_SPI
+#ifdef CONFIG_SYS_SC520_CDP_USE_SPI
        res = spi_eeprom_read(1, offset, buffer, len);
 #endif
-#ifdef CONFIG_SC520_CDP_USE_MW
+#ifdef CONFIG_SYS_SC520_CDP_USE_MW
        res = mw_eeprom_read(2, offset, buffer, len);
 #endif
-#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
+#if !defined(CONFIG_SYS_SC520_CDP_USE_SPI) && !defined(CONFIG_SYS_SC520_CDP_USE_MW)
        res = 0;
 #endif
        return res;
@@ -617,14 +619,19 @@ ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
                offset |= addr[i];
        }
 
-#ifdef CONFIG_SC520_CDP_USE_SPI
+#ifdef CONFIG_SYS_SC520_CDP_USE_SPI
        res = spi_eeprom_write(1, offset, buffer, len);
 #endif
-#ifdef CONFIG_SC520_CDP_USE_MW
+#ifdef CONFIG_SYS_SC520_CDP_USE_MW
        res = mw_eeprom_write(2, offset, buffer, len);
 #endif
-#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
+#if !defined(CONFIG_SYS_SC520_CDP_USE_SPI) && !defined(CONFIG_SYS_SC520_CDP_USE_MW)
        res = 0;
 #endif
        return res;
 }
+
+int board_eth_init(bd_t *bis)
+{
+       return pci_eth_init(bis);
+}