*
* Always return 1
*/
+#if defined(CONFIG_QS850)
+#define BOARD_IDENTITY "QS850"
+#elif defined(CONFIG_QS823)
+#define BOARD_IDENTITY "QS823"
+#else
+#define BOARD_IDENTITY "QS???"
+#endif
int checkboard (void)
{
- unsigned char *s, *e;
- unsigned char buf[64];
+ char *s, *e;
+ char buf[64];
int i;
- i = getenv_r("serial#", buf, sizeof(buf));
+ i = getenv_f("serial#", buf, sizeof(buf));
s = (i>0) ? buf : NULL;
-#ifdef CONFIG_QS850
- if (!s || strncmp(s, "QS850", 5)) {
- puts ("### No HW ID - assuming QS850");
-#endif
-#ifdef CONFIG_QS823
- if (!s || strncmp(s, "QS823", 5)) {
- puts ("### No HW ID - assuming QS823");
-#endif
+ if (!s || strncmp(s, BOARD_IDENTITY, 5)) {
+ puts ("### No HW ID - assuming " BOARD_IDENTITY);
} else {
for (e=s; *e; ++e) {
if (*e == ' ')
#define REFRESH_INIT_LOOPS (0)
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size;
/*
* Prescaler for refresh
*/
- memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
/*
* Map controller bank 1 to the SDRAM address
*/
- memctl->memc_or1 = CFG_OR1;
- memctl->memc_br1 = CFG_BR1;
+ memctl->memc_or1 = CONFIG_SYS_OR1;
+ memctl->memc_br1 = CONFIG_SYS_BR1;
udelay(1000);
/* perform SDRAM initialization sequence */
- memctl->memc_mamr = CFG_16M_MAMR;
+ memctl->memc_mamr = CONFIG_SYS_16M_MAMR;
udelay(100);
/* Program the SDRAM's Mode Register */
/*
* Check for 32M SDRAM Memory Size
*/
- size = dram_size(CFG_32M_MAMR|MAMR_PTAE,
- (ulong *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
+ size = dram_size(CONFIG_SYS_32M_MAMR|MAMR_PTAE,
+ (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
udelay (1000);
/*
* Check for 16M SDRAM Memory Size
*/
if (size != SDRAM_32M_MAX_SIZE) {
- size = dram_size(CFG_16M_MAMR|MAMR_PTAE,
- (ulong *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
+ size = dram_size(CONFIG_SYS_16M_MAMR|MAMR_PTAE,
+ (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
udelay (1000);
}
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- long int cnt, val;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- return (0);
- }
-
- for (cnt = 1; ; cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
- val = *addr;
-
- if (val != (~cnt)) {
- return (cnt * sizeof(long));
- }
- }
- /* NOTREACHED */
+ return (get_ram_size(base, maxsize));
}