]> git.kernelconcepts.de Git - karo-tx-uboot.git/blobdiff - board/st/stv0991/stv0991.c
karo: tx6: rework PMIC code to allow for different configs for same chip
[karo-tx-uboot.git] / board / st / stv0991 / stv0991.c
index bdeb53c1a70d12f9311d9ad1dbe20c2ee30c0c08..add1ce1a79a6f54e7994e50875e01dbee1010fa3 100644 (file)
@@ -9,9 +9,31 @@
 #include <miiphy.h>
 #include <asm/arch/stv0991_periph.h>
 #include <asm/arch/stv0991_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_pl01x.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct gpio_regs *const gpioa_regs =
+               (struct gpio_regs *) GPIOA_BASE_ADDR;
+
+#ifndef CONFIG_OF_CONTROL
+static const struct pl01x_serial_platdata serial_platdata = {
+       .base = 0x80406000,
+       .type = TYPE_PL011,
+       .clock = 2700 * 1000,
+};
+
+U_BOOT_DEVICE(stv09911_serials) = {
+       .name = "serial_pl01x",
+       .platdata = &serial_platdata,
+};
+#endif
+
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 void show_boot_progress(int progress)
 {
@@ -19,11 +41,34 @@ void show_boot_progress(int progress)
 }
 #endif
 
+void enable_eth_phy(void)
+{
+       /* Set GPIOA_06 pad HIGH (Appli board)*/
+       writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
+       writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
+}
+int board_eth_enable(void)
+{
+       stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
+       clock_setup(ETH_CLOCK_CFG);
+       enable_eth_phy();
+       return 0;
+}
+
+int board_qspi_enable(void)
+{
+       stv0991_pinmux_config(QSPI_CS_CLK_PAD);
+       clock_setup(QSPI_CLOCK_CFG);
+       return 0;
+}
+
 /*
  * Miscellaneous platform dependent initialisations
  */
 int board_init(void)
 {
+       board_eth_enable();
+       board_qspi_enable();
        return 0;
 }
 
@@ -33,6 +78,7 @@ int board_uart_init(void)
        clock_setup(UART_CLOCK_CFG);
        return 0;
 }
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
@@ -52,3 +98,17 @@ void dram_init_banksize(void)
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int ret = 0;
+
+#if defined(CONFIG_ETH_DESIGNWARE)
+       u32 interface = PHY_INTERFACE_MODE_MII;
+       if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
+               ret++;
+#endif
+       return ret;
+}
+#endif