ARM: keystone2: Cleanup PLL init code

[karo-tx-uboot.git] / board / ti / ks2_evm / board.c

diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index e1771d253a1e6dfc4d1dd2b490cd91a2e443af7b..859a26011c4c67d69b1524ca58883c5e43da0407 100644 (file)
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -13,6 +13,7 @@
 #include <exports.h>
 #include <fdt_support.h>
 #include <asm/arch/ddr3.h>
+#include <asm/arch/psc_defs.h>
 #include <asm/ti-common/ti-aemif.h>
 #include <asm/ti-common/keystone_net.h>
 
@@ -34,17 +35,20 @@ static struct aemif_config aemif_configs[] = {
 
 int dram_init(void)
 {
-       ddr3_init();
+       u32 ddr3_size;
+
+       ddr3_size = ddr3_init();
 
        gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
                                    CONFIG_MAX_RAM_BANK_SIZE);
        aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+       ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
        return 0;
 }
 
 int board_init(void)
 {
-       gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR;
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
        return 0;
 }
@@ -69,6 +73,14 @@ int board_eth_init(bd_t *bis)
        int port_num;
        char link_type_name[32];
 
+       /* By default, select PA PLL clock as PA clock source */
+       if (psc_enable_module(KS2_LPSC_PA))
+               return -1;
+       if (psc_enable_module(KS2_LPSC_CPGMAC))
+               return -1;
+       if (psc_enable_module(KS2_LPSC_CRYPTO))
+               return -1;
+
        port_num = get_num_eth_ports();
 
        for (j = 0; j < port_num; j++) {
@@ -103,7 +115,7 @@ u32 spl_boot_device(void)
 #endif
 
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
 {
        int lpae;
        char *env;
@@ -111,7 +123,6 @@ void ft_board_setup(void *blob, bd_t *bd)
        int nbanks;
        u64 size[2];
        u64 start[2];
-       char name[32];
        int nodeoffset;
        u32 ddr3a_size;
        int unitrd_fixup = 0;
@@ -147,15 +158,13 @@ void ft_board_setup(void *blob, bd_t *bd)
        }
 
        /* reserve memory at start of bank */
-       sprintf(name, "mem_reserve_head");
-       env = getenv(name);
+       env = getenv("mem_reserve_head");
        if (env) {
                start[0] += ustrtoul(env, &endp, 0);
                size[0] -= ustrtoul(env, &endp, 0);
        }
 
-       sprintf(name, "mem_reserve");
-       env = getenv(name);
+       env = getenv("mem_reserve");
        if (env)
                size[0] -= ustrtoul(env, &endp, 0);
 
@@ -209,6 +218,8 @@ void ft_board_setup(void *blob, bd_t *bd)
                        }
                }
        }
+
+       return 0;
 }
 
 void ft_board_setup_ex(void *blob, bd_t *bd)
@@ -244,5 +255,7 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
                        reserve_start += 2;
                }
        }
+
+       ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 }
 #endif