imported Freescale specific U-Boot additions for i.MX28,... release L2.6.31_10.08.01

[karo-tx-uboot.git] / cpu / arm920t / at91rm9200 / lowlevel_init.S

diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S
index 1902bd02c5d236e526d0bc2133b2c07dd954e843..d8bb96004b9797caf5d43e74bfe84668fe1e74a5 100755 (executable)
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -38,33 +38,7 @@
  * turn is based on the boot.bin code from ATMEL
  *
  */
-
-/* flash */
-#define MC_PUIA                0xFFFFFF10
-#define MC_PUP         0xFFFFFF50
-#define MC_PUER                0xFFFFFF54
-#define MC_ASR         0xFFFFFF04
-#define MC_AASR                0xFFFFFF08
-#define EBI_CFGR       0xFFFFFF64
-#define SMC2_CSR       0xFFFFFF70
-
-/* clocks */
-#define PLLAR          0xFFFFFC28
-#define PLLBR          0xFFFFFC2C
-#define MCKR           0xFFFFFC30
-
-#define AT91C_BASE_CKGR 0xFFFFFC20
-#define CKGR_MOR 0
-
-/* sdram */
-#define PIOC_ASR       0xFFFFF870
-#define PIOC_BSR       0xFFFFF874
-#define PIOC_PDR       0xFFFFF804
-#define EBI_CSA                0xFFFFFF60
-#define SDRC_CR                0xFFFFFF98
-#define SDRC_MR                0xFFFFFF90
-#define SDRC_TR                0xFFFFFF94
-
+#include <asm/arch/AT91RM9200.h>
 
 _MTEXT_BASE:
 #undef START_FROM_MEM
@@ -79,12 +53,12 @@ lowlevel_init:
        /* Get the CKGR Base Address */
        ldr     r1, =AT91C_BASE_CKGR
        /* Main oscillator Enable register */
-#ifdef CFG_USE_MAIN_OSCILLATOR
+#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
        ldr     r0, =0x0000FF01         /* Enable main oscillator,  OSCOUNT = 0xFF */
 #else
        ldr     r0, =0x0000FF00         /* Disable main oscillator, OSCOUNT = 0xFF */
 #endif
-       str     r0, [r1, #CKGR_MOR]
+       str     r0, [r1, #AT91C_CKGR_MOR]
        /* Add loop to compensate Main Oscillator startup time */
        ldr     r0, =0x00000010
 LoopOsc:
@@ -107,6 +81,7 @@ LoopOsc:
        bne     0b
        /* delay - this is all done by guess */
        ldr     r0, =0x00010000
+       /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
 1:
        subs    r0, r0, #1
        bhi     1b
@@ -134,72 +109,61 @@ LoopOsc:
        .ltorg
 
 SMRDATA:
-       .word MC_PUIA
-       .word MC_PUIA_VAL
-       .word MC_PUP
-       .word MC_PUP_VAL
-       .word MC_PUER
-       .word MC_PUER_VAL
-       .word MC_ASR
-       .word MC_ASR_VAL
-       .word MC_AASR
-       .word MC_AASR_VAL
-       .word EBI_CFGR
-       .word EBI_CFGR_VAL
-       .word SMC2_CSR
-       .word SMC2_CSR_VAL
-       .word PLLAR
-       .word PLLAR_VAL
-       .word PLLBR
-       .word PLLBR_VAL
-       .word MCKR
-       .word MCKR_VAL
-       /* SMRDATA is 80 bytes long */
-       /* here there's a delay of 100 */
+       .word AT91C_EBI_CFGR
+       .word CONFIG_SYS_EBI_CFGR_VAL
+       .word AT91C_SMC_CSR0
+       .word CONFIG_SYS_SMC_CSR0_VAL
+       .word AT91C_PLLAR
+       .word CONFIG_SYS_PLLAR_VAL
+       .word AT91C_PLLBR
+       .word CONFIG_SYS_PLLBR_VAL
+       .word AT91C_MCKR
+       .word CONFIG_SYS_MCKR_VAL
+       /* here there's a delay */
 SMRDATA1:
-       .word PIOC_ASR
-       .word PIOC_ASR_VAL
-       .word PIOC_BSR
-       .word PIOC_BSR_VAL
-       .word PIOC_PDR
-       .word PIOC_PDR_VAL
-       .word EBI_CSA
-       .word EBI_CSA_VAL
-       .word SDRC_CR
-       .word SDRC_CR_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL1
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL2
-       .word SDRAM1
-       .word SDRAM_VAL
-       .word SDRC_TR
-       .word SDRC_TR_VAL
-       .word SDRAM
-       .word SDRAM_VAL
-       .word SDRC_MR
-       .word SDRC_MR_VAL3
-       .word SDRAM
-       .word SDRAM_VAL
+       .word AT91C_PIOC_ASR
+       .word CONFIG_SYS_PIOC_ASR_VAL
+       .word AT91C_PIOC_BSR
+       .word CONFIG_SYS_PIOC_BSR_VAL
+       .word AT91C_PIOC_PDR
+       .word CONFIG_SYS_PIOC_PDR_VAL
+       .word AT91C_EBI_CSA
+       .word CONFIG_SYS_EBI_CSA_VAL
+       .word AT91C_SDRC_CR
+       .word CONFIG_SYS_SDRC_CR_VAL
+       .word AT91C_SDRC_MR
+       .word CONFIG_SYS_SDRC_MR_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word AT91C_SDRC_MR
+       .word CONFIG_SYS_SDRC_MR_VAL1
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word AT91C_SDRC_MR
+       .word CONFIG_SYS_SDRC_MR_VAL2
+       .word CONFIG_SYS_SDRAM1
+       .word CONFIG_SYS_SDRAM_VAL
+       .word AT91C_SDRC_TR
+       .word CONFIG_SYS_SDRC_TR_VAL
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
+       .word AT91C_SDRC_MR
+       .word CONFIG_SYS_SDRC_MR_VAL3
+       .word CONFIG_SYS_SDRAM
+       .word CONFIG_SYS_SDRAM_VAL
        /* SMRDATA1 is 176 bytes long */
 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */