applied patches from Freescale and Ka-Ro

[karo-tx-uboot.git] / cpu / arm_cortexa8 / cpu.c

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 5a5981e4054fada5a3aff183e18efed8844f7537..e4bd7cfb09fe581d5755433517a17f04443f06a3 100644 (file)
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -35,11 +35,97 @@
 #include <command.h>
 #include <asm/system.h>
 #include <asm/cache.h>
+#include <asm/cache-cp15.h>
+#include <asm/mmu.h>
+
 #ifndef CONFIG_L2_OFF
+#ifndef CONFIG_MXC
 #include <asm/arch/sys_proto.h>
 #endif
+#endif
 
-static void cache_flush(void);
+#define cache_flush(void)      \
+{      \
+       asm volatile (  \
+               "stmfd sp!, {r0-r5, r7, r9-r11};"       \
+               "mrc        p15, 1, r0, c0, c0, 1;" /*@ read clidr*/    \
+               /* @ extract loc from clidr */       \
+               "ands       r3, r0, #0x7000000;"        \
+               /* @ left align loc bit field*/      \
+               "mov        r3, r3, lsr #23;"   \
+               /* @ if loc is 0, then no need to clean*/    \
+               "beq        555f;" /* finished;" */     \
+               /* @ start clean at cache level 0*/  \
+               "mov        r10, #0;"   \
+               "111:" /*"loop1: */     \
+               /* @ work out 3x current cache level */ \
+               "add        r2, r10, r10, lsr #1;"      \
+               /* @ extract cache type bits from clidr */    \
+               "mov        r1, r0, lsr r2;"    \
+               /* @ mask of the bits for current cache only */ \
+               "and        r1, r1, #7;"        \
+               /* @ see what cache we have at this level*/  \
+               "cmp        r1, #2;"    \
+               /* @ skip if no cache, or just i-cache*/        \
+               "blt        444f;" /* skip;" */ \
+               /* @ select current cache level in cssr*/   \
+               "mcr        p15, 2, r10, c0, c0, 0;"    \
+               /* @ isb to sych the new cssr&csidr */  \
+               "mcr        p15, 0, r10, c7, c5, 4;"    \
+               /* @ read the new csidr */    \
+               "mrc        p15, 1, r1, c0, c0, 0;"     \
+               /* @ extract the length of the cache lines */ \
+               "and        r2, r1, #7;"        \
+               /* @ add 4 (line length offset) */   \
+               "add        r2, r2, #4;"        \
+               "ldr        r4, =0x3ff;"        \
+               /* @ find maximum number on the way size*/   \
+               "ands       r4, r4, r1, lsr #3;"        \
+               /*"clz  r5, r4;" @ find bit position of way size increment*/ \
+               ".word 0xE16F5F14;"     \
+               "ldr        r7, =0x7fff;"       \
+               /* @ extract max number of the index size*/  \
+               "ands       r7, r7, r1, lsr #13;"       \
+               "222:" /* loop2:"  */   \
+               /* @ create working copy of max way size*/   \
+               "mov        r9, r4;"    \
+               "333:" /* loop3:"  */   \
+               /* @ factor way and cache number into r11*/  \
+               "orr        r11, r10, r9, lsl r5;"      \
+               /* @ factor index number into r11*/  \
+               "orr        r11, r11, r7, lsl r2;"      \
+               /* @ clean & invalidate by set/way */   \
+               "mcr        p15, 0, r11, c7, c14, 2;"   \
+               /* @ decrement the way */       \
+               "subs       r9, r9, #1;"        \
+               "bge        333b;" /* loop3;" */        \
+               /* @ decrement the index */     \
+               "subs       r7, r7, #1;"        \
+               "bge        222b;" /* loop2;" */        \
+               "444:" /* skip: */      \
+               /*@ increment cache number */   \
+               "add        r10, r10, #2;"      \
+               "cmp        r3, r10;"   \
+               "bgt        111b;" /* loop1; */ \
+               "555:" /* "finished:" */        \
+               /* @ swith back to cache level 0 */     \
+               "mov        r10, #0;"   \
+               /* @ select current cache level in cssr */      \
+               "mcr        p15, 2, r10, c0, c0, 0;"    \
+               /* @ isb to sych the new cssr&csidr */  \
+               "mcr        p15, 0, r10, c7, c5, 4;"    \
+               "ldmfd      sp!, {r0-r5, r7, r9-r11};"  \
+               "666:" /* iflush:" */   \
+               "mov        r0, #0x0;"  \
+               /* @ invalidate I+BTB */        \
+               "mcr        p15, 0, r0, c7, c5, 0;"     \
+               /* @ drain WB */        \
+               "mcr        p15, 0, r0, c7, c10, 4;"    \
+               :       \
+               :       \
+               : "r0" /* Clobber list */       \
+       );      \
+}
 
 int cleanup_before_linux(void)
 {
@@ -53,13 +139,14 @@ int cleanup_before_linux(void)
         */
        disable_interrupts();
 
+       /* flush cache */
+       cache_flush();
+
        /* turn off I/D-cache */
        icache_disable();
+       /* invalidate D-cache */
        dcache_disable();
 
-       /* invalidate I-cache */
-       cache_flush();
-
 #ifndef CONFIG_L2_OFF
        /* turn off L2 cache */
        l2_cache_disable();
@@ -70,6 +157,9 @@ int cleanup_before_linux(void)
        /* mem barrier to sync up things */
        asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
 
+       /* turn off MMU */
+       MMU_OFF();
+
 #ifndef CONFIG_L2_OFF
        l2_cache_enable();
 #endif
@@ -77,7 +167,3 @@ int cleanup_before_linux(void)
        return 0;
 }
 
-static void cache_flush(void)
-{
-       asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
-}