* (C) Copyright 2005
* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <common.h>
#include <watchdog.h>
+#include <asm/immap.h>
-#ifdef CONFIG_M5271
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
#endif
-#ifdef CONFIG_M5272
-#include <asm/m5272.h>
-#include <asm/immap_5272.h>
+#ifndef CONFIG_M5272
+/* Only 5272 Flexbus chipselect is different from the rest */
+void init_fbcs(void)
+{
+ volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+ && defined(CONFIG_SYS_CS0_CTRL))
+ fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+ fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+ fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+#else
+#warning "Chip Select 0 are not initialized/used"
+#endif
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+ && defined(CONFIG_SYS_CS1_CTRL))
+ fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+ fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+ fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+ && defined(CONFIG_SYS_CS2_CTRL))
+ fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+ fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+ fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+ && defined(CONFIG_SYS_CS3_CTRL))
+ fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+ fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+ fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+ && defined(CONFIG_SYS_CS4_CTRL))
+ fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+ fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+ fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+ && defined(CONFIG_SYS_CS5_CTRL))
+ fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+ fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+ fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
+ && defined(CONFIG_SYS_CS6_CTRL))
+ fbcs->csar6 = CONFIG_SYS_CS6_BASE;
+ fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
+ fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
+ && defined(CONFIG_SYS_CS7_CTRL))
+ fbcs->csar7 = CONFIG_SYS_CS7_BASE;
+ fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
+ fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+#endif
+}
#endif
-#ifdef CONFIG_M5282
-#include <asm/m5282.h>
-#include <asm/immap_5282.h>
+#if defined(CONFIG_M5208)
+void cpu_init_f(void)
+{
+ volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+#ifndef CONFIG_WATCHDOG
+ volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+
+ /* Disable the watchdog if we aren't using it */
+ wdg->cr = 0;
#endif
-#ifdef CONFIG_M5249
-#include <asm/m5249.h>
+ scm1->mpr = 0x77777777;
+ scm1->pacra = 0;
+ scm1->pacrb = 0;
+ scm1->pacrc = 0;
+ scm1->pacrd = 0;
+ scm1->pacre = 0;
+ scm1->pacrf = 0;
+
+ /* FlexBus Chipselect */
+ init_fbcs();
+
+ icache_enable();
+}
+
+/* initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CONFIG_SYS_UART_PORT) {
+ case 0:
+ gpio->par_uart &= GPIO_PAR_UART0_MASK;
+ gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+ break;
+ case 1:
+ gpio->par_uart &= GPIO_PAR_UART0_MASK;
+ gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+ break;
+ case 2:
+#ifdef CONFIG_SYS_UART2_PRI_GPIO
+ gpio->par_timer &=
+ (GPIO_PAR_TMR_TIN0_MASK | GPIO_PAR_TMR_TIN1_MASK);
+ gpio->par_timer |=
+ (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+ gpio->par_feci2c &=
+ (GPIO_PAR_FECI2C_MDC_MASK | GPIO_PAR_FECI2C_MDIO_MASK);
+ gpio->par_feci2c |=
+ (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+#endif
+#ifdef CONFIG_SYS_UART2_ALT1_GPIO
+ gpio->par_feci2c &=
+ (GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
+ gpio->par_feci2c |=
+ (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
#endif
+ break;
+ }
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if (setclear) {
+ gpio->par_fec |=
+ GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
+ gpio->par_feci2c |=
+ GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+ } else {
+ gpio->par_fec &=
+ (GPIO_PAR_FEC_7W_MASK & GPIO_PAR_FEC_MII_MASK);
+ gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_MASK;
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
+#endif /* CONFIG_M5208 */
+
+#if defined(CONFIG_M5253)
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
+ mbar_writeByte(MCFSIM_SYPCR, 0x00);
+ mbar_writeByte(MCFSIM_SWIVR, 0x0f);
+ mbar_writeByte(MCFSIM_SWSR, 0x00);
+ mbar_writeByte(MCFSIM_SWDICR, 0x00);
+ mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
+ mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
+ mbar_writeByte(MCFSIM_I2CICR, 0x00);
+ mbar_writeByte(MCFSIM_UART1ICR, 0x00);
+ mbar_writeByte(MCFSIM_UART2ICR, 0x00);
+ mbar_writeByte(MCFSIM_ICR6, 0x00);
+ mbar_writeByte(MCFSIM_ICR7, 0x00);
+ mbar_writeByte(MCFSIM_ICR8, 0x00);
+ mbar_writeByte(MCFSIM_ICR9, 0x00);
+ mbar_writeByte(MCFSIM_QSPIICR, 0x00);
+
+ mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
+ mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
+ mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
+
+ /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
+
+ /* FlexBus Chipselect */
+ init_fbcs();
+
+#ifdef CONFIG_FSL_I2C
+ CONFIG_SYS_I2C_PINMUX_REG =
+ CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
+ CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+#ifdef CONFIG_SYS_I2C2_OFFSET
+ CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
+ CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
+#endif
+#endif
+
+ /* enable instruction cache now */
+ icache_enable();
+}
+
+/*initialize higher level parts of CPU like timers */
+int cpu_init_r(void)
+{
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ /* Setup Ports: */
+ switch (CONFIG_SYS_UART_PORT) {
+ case 0:
+ break;
+ case 1:
+ break;
+ case 2:
+ break;
+ }
+}
+#endif /* #if defined(CONFIG_M5253) */
#if defined(CONFIG_M5271)
-void cpu_init_f (void)
+void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
/* Disable the watchdog if we aren't using it */
mbar_writeShort(MCF_WTM_WCR, 0);
#endif
+ /* FlexBus Chipselect */
+ init_fbcs();
+
+#ifdef CONFIG_SYS_MCF_SYNCR
+ /* Set clockspeed according to board header file */
+ mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
+#else
/* Set clockspeed to 100MHz */
- mbar_writeShort(MCF_FMPLL_SYNCR,
+ mbar_writeLong(MCF_FMPLL_SYNCR,
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
- while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK);
-
- /* Enable UART pins */
- mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
- MCF_GPIO_PAR_UART_U0RXD |
- MCF_GPIO_PAR_UART_U1RXD_UART1 |
- MCF_GPIO_PAR_UART_U1TXD_UART1);
-
- /* Enable Ethernet pins */
- mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+#endif
+ while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
}
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
return (0);
}
+
+void uart_port_conf(void)
+{
+ /* Setup Ports: */
+ switch (CONFIG_SYS_UART_PORT) {
+ case 0:
+ mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
+ MCF_GPIO_PAR_UART_U0RXD);
+ break;
+ case 1:
+ mbar_writeShort(MCF_GPIO_PAR_UART,
+ MCF_GPIO_PAR_UART_U1RXD_UART1 |
+ MCF_GPIO_PAR_UART_U1TXD_UART1);
+ break;
+ case 2:
+ mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
+ break;
+ }
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ if (setclear) {
+ /* Enable Ethernet pins */
+ mbar_writeByte(MCF_GPIO_PAR_FECI2C,
+ (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
+ } else {
+ }
+
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
#endif
#if defined(CONFIG_M5272)
* initialize a bunch of registers,
* initialize the UPM's
*/
-void cpu_init_f (void)
+void cpu_init_f(void)
{
/* if we come from RAM we assume the CPU is
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- volatile immap_t *regp = (immap_t *)CFG_MBAR;
-
- volatile unsigned char *mbar;
- mbar = (volatile unsigned char *) CFG_MBAR;
+ volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+ volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
+ volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
- regp->sysctrl_reg.sc_scr = CFG_SCR;
- regp->sysctrl_reg.sc_spr = CFG_SPR;
+ sysctrl->sc_scr = CONFIG_SYS_SCR;
+ sysctrl->sc_spr = CONFIG_SYS_SPR;
/* Setup Ports: */
- regp->gpio_reg.gpio_pacnt = CFG_PACNT;
- regp->gpio_reg.gpio_paddr = CFG_PADDR;
- regp->gpio_reg.gpio_padat = CFG_PADAT;
- regp->gpio_reg.gpio_pbcnt = CFG_PBCNT;
- regp->gpio_reg.gpio_pbddr = CFG_PBDDR;
- regp->gpio_reg.gpio_pbdat = CFG_PBDAT;
- regp->gpio_reg.gpio_pdcnt = CFG_PDCNT;
+ gpio->gpio_pacnt = CONFIG_SYS_PACNT;
+ gpio->gpio_paddr = CONFIG_SYS_PADDR;
+ gpio->gpio_padat = CONFIG_SYS_PADAT;
+ gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
+ gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
+ gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
+ gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
/* Memory Controller: */
- regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM;
- regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM;
+ csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
+ csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
-#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
- regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM;
- regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM;
+#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
+ csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
+ csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
#endif
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
- regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM;
- regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM;
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+ csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
+ csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
#endif
-#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
- regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM;
- regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM;
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+ csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
+ csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
#endif
-#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
- regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM;
- regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM;
+#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
+ csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
+ csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
#endif
-#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
- regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM;
- regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM;
+#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
+ csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
+ csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
#endif
-#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
- regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM;
- regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM;
+#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
+ csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
+ csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
#endif
-#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
- regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM;
- regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM;
+#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
+ csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
+ csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
#endif
-#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
+#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
/* enable instruction cache now */
icache_enable();
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
+{
+ return (0);
+}
+
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CONFIG_SYS_UART_PORT) {
+ case 0:
+ gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
+ gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
+ break;
+ case 1:
+ gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
+ gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
+ break;
+ }
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if (setclear) {
+ gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
+ GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
+ GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+ GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+ } else {
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
+#endif /* #if defined(CONFIG_M5272) */
+
+#if defined(CONFIG_M5275)
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ /*
+ * if we come from RAM we assume the CPU is
+ * already initialized.
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+ volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+ volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
+
+ /* Kill watchdog so we can initialize the PLL */
+ wdog_reg->wcr = 0;
+
+ /* FlexBus Chipselect */
+ init_fbcs();
+#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
+
+#ifdef CONFIG_FSL_I2C
+ CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
+ CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+#endif
+
+ /* enable instruction cache now */
+ icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
{
return (0);
}
-#endif /* #if defined(CONFIG_M5272) */
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CONFIG_SYS_UART_PORT) {
+ case 0:
+ gpio->par_uart |= UART0_ENABLE_MASK;
+ break;
+ case 1:
+ gpio->par_uart |= UART1_ENABLE_MASK;
+ break;
+ case 2:
+ gpio->par_uart |= UART2_ENABLE_MASK;
+ break;
+ }
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ struct fec_info_s *info = (struct fec_info_s *) dev->priv;
+ volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+ if (setclear) {
+ /* Enable Ethernet pins */
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_feci2c |= 0x0F00;
+ gpio->par_fec0hl |= 0xC0;
+ } else {
+ gpio->par_feci2c |= 0x00A0;
+ gpio->par_fec1hl |= 0xC0;
+ }
+ } else {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_feci2c &= ~0x0F00;
+ gpio->par_fec0hl &= ~0xC0;
+ } else {
+ gpio->par_feci2c &= ~0x00A0;
+ gpio->par_fec1hl &= ~0xC0;
+ }
+ }
+
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
+#endif /* #if defined(CONFIG_M5275) */
-#ifdef CONFIG_M5282
+#if defined(CONFIG_M5282)
/*
* Breath some life into the CPU...
*
* initialize a bunch of registers,
* initialize the UPM's
*/
-void cpu_init_f (void)
+void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
/* disable watchdog if we aren't using it */
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
- MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
+ MCFCLOCK_SYNCR =
+ MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
+ MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
+ while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
+
+ MCFGPIO_PBCDPAR = 0xc0;
/* Set up the GPIO ports */
-#ifdef CFG_PEPAR
- MCFGPIO_PEPAR = CFG_PEPAR;
+#ifdef CONFIG_SYS_PEPAR
+ MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
#endif
-#ifdef CFG_PFPAR
- MCFGPIO_PFPAR = CFG_PFPAR;
+#ifdef CONFIG_SYS_PFPAR
+ MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
#endif
-#ifdef CFG_PJPAR
- MCFGPIO_PJPAR = CFG_PJPAR;
+#ifdef CONFIG_SYS_PJPAR
+ MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
#endif
-#ifdef CFG_PSDPAR
- MCFGPIO_PSDPAR = CFG_PSDPAR;
+#ifdef CONFIG_SYS_PSDPAR
+ MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
#endif
-#ifdef CFG_PASPAR
- MCFGPIO_PASPAR = CFG_PASPAR;
+#ifdef CONFIG_SYS_PASPAR
+ MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
#endif
-#ifdef CFG_PEHLPAR
- MCFGPIO_PEHLPAR = CFG_PEHLPAR;
+#ifdef CONFIG_SYS_PEHLPAR
+ MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
#endif
-#ifdef CFG_PQSPAR
- MCFGPIO_PQSPAR = CFG_PQSPAR;
+#ifdef CONFIG_SYS_PQSPAR
+ MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
#endif
-#ifdef CFG_PTCPAR
- MCFGPIO_PTCPAR = CFG_PTCPAR;
+#ifdef CONFIG_SYS_PTCPAR
+ MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
#endif
-#ifdef CFG_PTDPAR
- MCFGPIO_PTDPAR = CFG_PTDPAR;
+#ifdef CONFIG_SYS_PTDPAR
+ MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
#endif
-#ifdef CFG_PUAPAR
- MCFGPIO_PUAPAR = CFG_PUAPAR;
+#ifdef CONFIG_SYS_PUAPAR
+ MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
#endif
-#ifdef CFG_DDRUA
- MCFGPIO_DDRUA = CFG_DDRUA;
+#ifdef CONFIG_SYS_DDRUA
+ MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
#endif
- /* This is probably a bad place to setup chip selects, but everyone
- else is doing it! */
-
-#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
- defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
- defined(CFG_CS0_WS)
-
- MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
-
- #if (CFG_CS0_WIDTH == 8)
- #define CFG_CS0_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS0_WIDTH == 16)
- #define CFG_CS0_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS0_WIDTH == 32)
- #define CFG_CS0_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
- #endif
- MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
- |CFG_CS0_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS0_RO != 0)
- MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
- |MCFCSM_CSMR_WP|MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V;
- #endif
-#else
- #waring "Chip Select 0 are not initialized/used"
-#endif
-
-#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
- defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
- defined(CFG_CS1_WS)
-
- MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
-
- #if (CFG_CS1_WIDTH == 8)
- #define CFG_CS1_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS1_WIDTH == 16)
- #define CFG_CS1_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS1_WIDTH == 32)
- #define CFG_CS1_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
- #endif
- MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
- |CFG_CS1_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS1_RO != 0)
- MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
- |MCFCSM_CSMR_WP
- |MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
- |MCFCSM_CSMR_V;
- #endif
-#else
- #warning "Chip Select 1 are not initialized/used"
-#endif
-
-#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
- defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
- defined(CFG_CS2_WS)
-
- MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
-
- #if (CFG_CS2_WIDTH == 8)
- #define CFG_CS2_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS2_WIDTH == 16)
- #define CFG_CS2_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS2_WIDTH == 32)
- #define CFG_CS2_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
- #endif
- MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
- |CFG_CS2_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS2_RO != 0)
- MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
- |MCFCSM_CSMR_WP
- |MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
- |MCFCSM_CSMR_V;
- #endif
-#else
- #warning "Chip Select 2 are not initialized/used"
-#endif
-
-#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
- defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
- defined(CFG_CS3_WS)
-
- MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
-
- #if (CFG_CS3_WIDTH == 8)
- #define CFG_CS3_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS3_WIDTH == 16)
- #define CFG_CS3_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS3_WIDTH == 32)
- #define CFG_CS3_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
- #endif
- MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
- |CFG_CS3_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS3_RO != 0)
- MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
- |MCFCSM_CSMR_WP
- |MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
- |MCFCSM_CSMR_V;
- #endif
-#else
- #warning "Chip Select 3 are not initialized/used"
-#endif
+ /* FlexBus Chipselect */
+ init_fbcs();
-#endif /* CONFIG_MONITOR_IS_IN_RAM */
+#endif /* CONFIG_MONITOR_IS_IN_RAM */
/* defer enabling cache until boot (see do_go) */
/* icache_enable(); */
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
return (0);
}
+
+void uart_port_conf(void)
+{
+ /* Setup Ports: */
+ switch (CONFIG_SYS_UART_PORT) {
+ case 0:
+ MCFGPIO_PUAPAR &= 0xFc;
+ MCFGPIO_PUAPAR |= 0x03;
+ break;
+ case 1:
+ MCFGPIO_PUAPAR &= 0xF3;
+ MCFGPIO_PUAPAR |= 0x0C;
+ break;
+ case 2:
+ MCFGPIO_PASPAR &= 0xFF0F;
+ MCFGPIO_PASPAR |= 0x00A0;
+ break;
+ }
+}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ if (setclear) {
+ MCFGPIO_PASPAR |= 0x0F00;
+ MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+ } else {
+ MCFGPIO_PASPAR &= 0xF0FF;
+ MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
#endif
#if defined(CONFIG_M5249)
* initialize a bunch of registers,
* initialize the UPM's
*/
-void cpu_init_f (void)
+void cpu_init_f(void)
{
-#ifndef CFG_PLL_BYPASS
- /*
- * Setup the PLL to run at the specified speed
- *
- */
- volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
- unsigned long pllcr;
-#ifdef CFG_FAST_CLK
- pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
-#else
- pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
-#endif
- cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
- mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
- mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
- pllcr ^= 0x00000001; /* Set pll bypass to 1 */
- mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
- udelay(0x20); /* Wait for a lock ... */
-#endif /* #ifndef CFG_PLL_BYPASS */
-
/*
* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
- * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
- * which is their primary function.
- * ~Jeremy
+ * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
+ * which is their primary function.
+ * ~Jeremy
*/
- mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
- mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
- mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
- mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
- mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
- mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
+ mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
+ mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
+ mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
+ mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
/*
* dBug Compliance:
* ~Jeremy
*
*/
- mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
+ mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
mbar_writeByte(MCFSIM_SYPCR, 0x00);
mbar_writeByte(MCFSIM_SWIVR, 0x0f);
mbar_writeByte(MCFSIM_SWSR, 0x00);
mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
- mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
+ mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
/* Setup interrupt priorities for gpio7 */
/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
- /*
- * Setup chip selects...
- */
-
- mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
- mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
- mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
-
- mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
- mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
- mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
+ /* FlexBus Chipselect */
+ init_fbcs();
/* enable instruction cache now */
icache_enable();
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
return (0);
}
-#endif /* #if defined(CONFIG_M5249) */
+
+void uart_port_conf(void)
+{
+ /* Setup Ports: */
+ switch (CONFIG_SYS_UART_PORT) {
+ case 0:
+ break;
+ case 1:
+ break;
+ }
+}
+#endif /* #if defined(CONFIG_M5249) */
projects / karo-tx-uboot.git / blobdiff