Prepare for 0.3.0 release

[karo-tx-uboot.git] / cpu / mips / cache.S

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 2715b9b025c06d0802b51dbb14ca820837d48498..55daa89e7290d555622f163e3c1b77ee53aba663 100644 (file)
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -250,12 +250,17 @@ dcache_disable:
 * RETURNS: N/A
 *
 */
+#if defined(CONFIG_INCA_IP)
+# define       CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
+#elif defined(CONFIG_PURPLE)
+# define       CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
+#endif
        .globl  mips_cache_lock
        .ent    mips_cache_lock
 mips_cache_lock:
-       li      a1, K0BASE - CFG_DCACHE_SIZE/2
+       li      a1, K0BASE - CACHE_LOCK_SIZE
        addu    a0, a1
-       li      a2, CFG_DCACHE_SIZE/2
+       li      a2, CACHE_LOCK_SIZE
        li      a3, CFG_CACHELINE_SIZE
        move    a1, a2
        icacheop(a0,a1,a2,a3,0x1d)