rename CFG_ macros to CONFIG_SYS

[karo-tx-uboot.git] / cpu / mpc8220 / dramSetup.c

diff --git a/cpu/mpc8220/dramSetup.c b/cpu/mpc8220/dramSetup.c
index 90a7183106ebf61e0d0a24083eee11acae84fb3c..52cf1333f7973efae018b2c6ffbbd528a774cf2a 100644 (file)
--- a/cpu/mpc8220/dramSetup.c
+++ b/cpu/mpc8220/dramSetup.c
@@ -32,9 +32,11 @@ characteristics to initialize the dram on MPC8220
 #include "i2cCore.h"
 #include "dramSetup.h"
 
-#define SPD_SIZE       CFG_SDRAM_SPD_SIZE
-#define DRAM_SPD       (CFG_SDRAM_SPD_I2C_ADDR)<<1     /* on Board SPD eeprom */
-#define TOTAL_BANK     CFG_SDRAM_TOTAL_BANKS
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SPD_SIZE       CONFIG_SYS_SDRAM_SPD_SIZE
+#define DRAM_SPD       (CONFIG_SYS_SDRAM_SPD_I2C_ADDR)<<1      /* on Board SPD eeprom */
+#define TOTAL_BANK     CONFIG_SYS_SDRAM_TOTAL_BANKS
 
 int spd_status (volatile i2c8220_t * pi2c, u8 sta_bit, u8 truefalse)
 {
@@ -91,8 +93,6 @@ int spd_readbyte (volatile i2c8220_t * pi2c, u8 * readb, int *index)
 
 int readSpdData (u8 * spdData)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        volatile i2c8220_t *pi2cReg;
        volatile pcfg8220_t *pcfg;
        u8 slvAdr = DRAM_SPD;
@@ -103,7 +103,7 @@ int readSpdData (u8 * spdData)
        /* Enable Port Configuration for SDA and SDL signals */
        pcfg = (volatile pcfg8220_t *) (MMAP_PCFG);
        __asm__ ("sync");
-       pcfg->pcfg3 &= ~CFG_I2C_PORT3_CONFIG;
+       pcfg->pcfg3 &= ~CONFIG_SYS_I2C_PORT3_CONFIG;
        __asm__ ("sync");
 
        /* Points the structure to I2c mbar memory offset */
@@ -144,7 +144,7 @@ int readSpdData (u8 * spdData)
                break;
        }
 
-       pi2cReg->adr = CFG_I2C_SLAVE<<1;
+       pi2cReg->adr = CONFIG_SYS_I2C_SLAVE<<1;
 
        pi2cReg->cr = I2C_CTL_EN;       /* Set Enable         */
 
@@ -403,8 +403,6 @@ u8 checkMuxSetting (u8 rows, u8 columns)
 
 u32 dramSetup (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        draminfo_t DramInfo[TOTAL_BANK];
        draminfo_t *pDramInfo;
        u32 size, temp, cfg_value, mode_value, refresh;
@@ -543,12 +541,7 @@ u32 dramSetup (void)
        }
 
        /* Set up the Drive Strength register */
-       temp = ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT)
-               | (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT)
-               | (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT)
-               | (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT)
-               | (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT));
-       sysconf->sdramds = temp;
+       sysconf->sdramds = CONFIG_SYS_SDRAM_DRIVE_STRENGTH;
 
        /* ********************** Cfg 1 ************************* */
 
@@ -686,7 +679,7 @@ u32 dramSetup (void)
 
 
        /* Set up mode value for CAS latency */
-#if (CFG_SDRAM_CAS_LATENCY==5) /* CL=2.5 */
+#if (CONFIG_SYS_SDRAM_CAS_LATENCY==5) /* CL=2.5 */
        mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) |
                MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2p5) | MODE_CMD);
 #else