imported Ka-Ro specific additions to U-Boot 2009.08 for TX28

[karo-tx-uboot.git] / cpu / pxa / cpu.c

diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index 0ee8180361f5f43e5fcbb066d52d6e87e211a9e1..800d120e718bb11a6527223fec3b94855ec17988 100755 (executable)
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -33,22 +33,9 @@
 #include <common.h>
 #include <command.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-int cpu_init (void)
-{
-       /*
-        * setup up stacks if necessary
-        */
-#ifdef CONFIG_USE_IRQ
-       IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
-       FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-       return 0;
-}
+static void cache_flush(void);
 
 int cleanup_before_linux (void)
 {
@@ -59,92 +46,26 @@ int cleanup_before_linux (void)
         * just disable everything that can disturb booting linux
         */
 
-       unsigned long i;
-
        disable_interrupts ();
 
        /* turn off I-cache */
-       asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-       i &= ~0x1000;
-       asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+       icache_disable();
+       dcache_disable();
 
        /* flush I-cache */
-       asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+       cache_flush();
 
        return (0);
 }
 
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-       printf ("resetting ...\n");
+       unsigned long i = 0;
 
-       udelay (50000);                         /* wait 50 ms */
-       disable_interrupts ();
-       reset_cpu (0);
-
-       /*NOTREACHED*/
-       return (0);
-}
-
-/* taken from blob */
-void icache_enable (void)
-{
-       register u32 i;
-
-       /* read control register */
-       asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
-       /* set i-cache */
-       i |= 0x1000;
-
-       /* write back to control register */
-       asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-}
-
-void icache_disable (void)
-{
-       register u32 i;
-
-       /* read control register */
-       asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
-       /* clear i-cache */
-       i &= ~0x1000;
-
-       /* write back to control register */
-       asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
-       /* flush i-cache */
        asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
 }
 
-int icache_status (void)
-{
-       register u32 i;
-
-       /* read control register */
-       asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-
-       /* return bit */
-       return (i & 0x1000);
-}
-
-/* we will never enable dcache, because we have to setup MMU first */
-void dcache_enable (void)
-{
-       return;
-}
-
-void dcache_disable (void)
-{
-       return;
-}
-
-int dcache_status (void)
-{
-       return 0;                                       /* always off */
-}
-
 #ifndef CONFIG_CPU_MONAHANS
 void set_GPIO_mode(int gpio_mode)
 {