* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
* Terry Lv <r65388@freescale.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- *
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <libata.h>
#include <ahci.h>
#include <fis.h>
+#include <sata.h>
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
#include "dwc_ahsata.h"
struct sata_port_regs {
static int is_ready;
-static inline u32 ahci_port_base(u32 base, u32 port)
+static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
{
return base + 0x100 + (port * 0x80);
}
for (i = 0; i < probe_ent->n_ports; i++) {
probe_ent->port[i].port_mmio =
- ahci_port_base((u32)host_mmio, i);
+ ahci_port_base(host_mmio, i);
port_mmio =
(struct sata_port_regs *)probe_ent->port[i].port_mmio;
| ATA_FLAG_PIO_DMA
| ATA_FLAG_NO_ATAPI;
- probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR;
+ probe_ent->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
/* initialize adapter */
rc = ahci_host_init(probe_ent);
memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
cmd_hdr->opts = cpu_to_le32(opts);
cmd_hdr->status = 0;
- cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
- cmd_hdr->tbl_addr_hi = 0;
+ pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
+#ifdef CONFIG_PHYS_64BIT
+ pp->cmd_slot->tbl_addr_hi =
+ cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
+#endif
}
#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
if (buf && buf_len)
sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len);
opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
- if (is_write)
+ if (is_write) {
opts |= 0x40;
+ flush_cache((ulong)buf, buf_len);
+ }
ahci_fill_cmd_slot(pp, cmd_slot, opts);
+ flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
printf("timeout exit!\n");
return -1;
}
+ invalidate_dcache_range((int)(pp->cmd_slot),
+ (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
debug("ahci_exec_ata_cmd: %d byte transferred.\n",
pp->cmd_slot->status);
+ if (!is_write)
+ invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
return buf_len;
}
{
struct ahci_probe_ent *probe_ent =
(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d, *cfis = &h2d;
+ struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+ struct sata_fis_h2d *cfis = &h2d;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
* and its scatter-gather table
*/
pp->cmd_tbl = mem;
- debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
+ debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
mem += AHCI_CMD_TBL_HDR;
u32 linkmap;
struct ahci_probe_ent *probe_ent = NULL;
+#if defined(CONFIG_ARCH_MX6)
+ if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ return 1;
+#endif
if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
printf("The sata index %d is out of ranges\n\r", dev);
return -1;
return 0;
}
+int reset_sata(int dev)
+{
+ struct ahci_probe_ent *probe_ent;
+ struct sata_host_regs *host_mmio;
+
+ if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
+ printf("The sata index %d is out of ranges\n\r", dev);
+ return -1;
+ }
+
+ probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+ if (NULL == probe_ent)
+ /* not initialized, so nothing to reset */
+ return 0;
+
+ host_mmio = (struct sata_host_regs *)probe_ent->mmio_base;
+ setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
+ while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
+ udelay(100);
+
+ return 0;
+}
+
static void dwc_ahsata_print_info(int dev)
{
block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
{
struct ahci_probe_ent *probe_ent =
(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d, *cfis = &h2d;
+ struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+ struct sata_fis_h2d *cfis = &h2d;
u8 port = probe_ent->hard_port_no;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
{
struct ahci_probe_ent *probe_ent =
(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d, *cfis = &h2d;
+ struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+ struct sata_fis_h2d *cfis = &h2d;
u8 port = probe_ent->hard_port_no;
u32 block;
{
struct ahci_probe_ent *probe_ent =
(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d, *cfis = &h2d;
+ struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+ struct sata_fis_h2d *cfis = &h2d;
u8 port = probe_ent->hard_port_no;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
{
struct ahci_probe_ent *probe_ent =
(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d, *cfis = &h2d;
+ struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+ struct sata_fis_h2d *cfis = &h2d;
u8 port = probe_ent->hard_port_no;
u64 block;
{
struct ahci_probe_ent *probe_ent =
(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d, *cfis = &h2d;
+ struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+ struct sata_fis_h2d *cfis = &h2d;
u8 port = probe_ent->hard_port_no;
u64 block;
{
struct ahci_probe_ent *probe_ent =
(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
- struct sata_fis_h2d h2d, *cfis = &h2d;
+ struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
+ struct sata_fis_h2d *cfis = &h2d;
u8 port = probe_ent->hard_port_no;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
}
u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
- void *buffer, int is_write)
+ const void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
}
u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
- void *buffer, int is_write)
+ const void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
return blkcnt;
}
+int sata_port_status(int dev, int port)
+{
+ struct sata_port_regs *port_mmio;
+ struct ahci_probe_ent *probe_ent = NULL;
+
+ if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
+ return -EINVAL;
+
+ if (sata_dev_desc[dev].priv == NULL)
+ return -ENODEV;
+
+ probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+ port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio;
+
+ return readl(&(port_mmio->ssts)) & SATA_PORT_SSTS_DET_MASK;
+}
+
/*
* SATA interface between low level driver and command layer
*/
-ulong sata_read(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
u32 rc;
return rc;
}
-ulong sata_write(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
u32 rc;
struct ahci_probe_ent *probe_ent =
u8 port = probe_ent->hard_port_no;
block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
- id = (u16 *)malloc(ATA_ID_WORDS * 2);
+ id = (u16 *)memalign(ARCH_DMA_MINALIGN,
+ roundup(ARCH_DMA_MINALIGN,
+ (ATA_ID_WORDS * 2)));
if (!id) {
printf("id malloc failed\n\r");
return -1;
projects / karo-tx-uboot.git / blobdiff