ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL

[karo-tx-uboot.git] / drivers / ddr / altera / sequencer.c

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index dd7256692d6845e1965569f2877e1b845294944f..f6414e02c7483e4da3827db4ce2e079088a38a88 100644 (file)
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -966,8 +966,8 @@ static void rw_mgr_mem_initialize(void)
         * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
         * b = 6A
         */
-       rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
-                                 SEQ_TINIT_CNTR2_VAL,
+       rw_mgr_mem_init_load_regs(TINIT_CNTR0_VAL, TINIT_CNTR1_VAL,
+                                 TINIT_CNTR2_VAL,
                                  rwcfg->init_reset_0_cke_0);
 
        /* Indicate that memory is stable. */
@@ -987,8 +987,8 @@ static void rw_mgr_mem_initialize(void)
         * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
         * b = FF
         */
-       rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
-                                 SEQ_TRESET_CNTR2_VAL,
+       rw_mgr_mem_init_load_regs(TRESET_CNTR0_VAL, TRESET_CNTR1_VAL,
+                                 TRESET_CNTR2_VAL,
                                  rwcfg->init_reset_1_cke_0);
 
        /* Bring up clock enable. */