Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

[karo-tx-uboot.git] / drivers / mtd / nand / s3c2410_nand.c

diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index 9f02dd8f11839053e9f2cc306926d25e78fd29a8..1187b9fee4e9feb2272a9d3bd412cd0e7f395dd9 100644 (file)
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -21,7 +21,7 @@
 #include <common.h>
 
 #include <nand.h>
-#include <asm/arch/s3c2410.h>
+#include <asm/arch/s3c24x0_cpu.h>
 #include <asm/io.h>
 
 #define S3C2410_NFCONF_EN          (1<<15)
@@ -36,12 +36,27 @@
 #define S3C2410_ADDR_NALE 4
 #define S3C2410_ADDR_NCLE 8
 
+#ifdef CONFIG_NAND_SPL
+
+/* in the early stage of NAND flash booting, printf() is not available */
+#define printf(fmt, args...)
+
+static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+       int i;
+       struct nand_chip *this = mtd->priv;
+
+       for (i = 0; i < len; i++)
+               buf[i] = readb(this->IO_ADDR_R);
+}
+#endif
+
 static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
        struct nand_chip *chip = mtd->priv;
        struct s3c2410_nand *nand = s3c2410_get_base_nand();
 
-       debugX(1, "hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
+       debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
 
        if (ctrl & NAND_CTRL_CHANGE) {
                ulong IO_ADDR_W = (ulong)nand;
@@ -54,11 +69,11 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
                chip->IO_ADDR_W = (void *)IO_ADDR_W;
 
                if (ctrl & NAND_NCE)
-                       writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE,
-                              &nand->NFCONF);
+                       writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE,
+                              &nand->nfconf);
                else
-                       writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE,
-                              &nand->NFCONF);
+                       writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE,
+                              &nand->nfconf);
        }
 
        if (cmd != NAND_CMD_NONE)
@@ -68,25 +83,26 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 static int s3c2410_dev_ready(struct mtd_info *mtd)
 {
        struct s3c2410_nand *nand = s3c2410_get_base_nand();
-       debugX(1, "dev_ready\n");
-       return readl(&nand->NFSTAT) & 0x01;
+       debug("dev_ready\n");
+       return readl(&nand->nfstat) & 0x01;
 }
 
 #ifdef CONFIG_S3C2410_NAND_HWECC
 void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 {
        struct s3c2410_nand *nand = s3c2410_get_base_nand();
-       debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
-       writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF);
+       debug("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
+       writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf);
 }
 
 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
                                      u_char *ecc_code)
 {
-       ecc_code[0] = NFECC0;
-       ecc_code[1] = NFECC1;
-       ecc_code[2] = NFECC2;
-       debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
+       struct s3c2410_nand *nand = s3c2410_get_base_nand();
+       ecc_code[0] = readb(&nand->nfecc);
+       ecc_code[1] = readb(&nand->nfecc + 1);
+       ecc_code[2] = readb(&nand->nfecc + 2);
+       debug("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
               mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
 
        return 0;
@@ -112,26 +128,38 @@ int board_nand_init(struct nand_chip *nand)
        struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
        struct s3c2410_nand *nand_reg = s3c2410_get_base_nand();
 
-       debugX(1, "board_nand_init()\n");
+       debug("board_nand_init()\n");
 
-       writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+       writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
 
        /* initialize hardware */
-       twrph0 = 3;
-       twrph1 = 0;
-       tacls = 0;
+#if defined(CONFIG_S3C24XX_CUSTOM_NAND_TIMING)
+       tacls  = CONFIG_S3C24XX_TACLS;
+       twrph0 = CONFIG_S3C24XX_TWRPH0;
+       twrph1 =  CONFIG_S3C24XX_TWRPH1;
+#else
+       tacls = 4;
+       twrph0 = 8;
+       twrph1 = 8;
+#endif
 
        cfg = S3C2410_NFCONF_EN;
        cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
        cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
        cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
-       writel(cfg, &nand_reg->NFCONF);
+       writel(cfg, &nand_reg->nfconf);
 
        /* initialize nand_chip data structure */
-       nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA;
+       nand->IO_ADDR_R = (void *)&nand_reg->nfdata;
+       nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
+
+       nand->select_chip = NULL;
 
        /* read_buf and write_buf are default */
        /* read_byte and write_byte are default */
+#ifdef CONFIG_NAND_SPL
+       nand->read_buf = nand_read_buf;
+#endif
 
        /* hwcontrol always must be implemented */
        nand->cmd_ctrl = s3c2410_hwcontrol;
@@ -142,18 +170,19 @@ int board_nand_init(struct nand_chip *nand)
        nand->ecc.hwctl = s3c2410_nand_enable_hwecc;
        nand->ecc.calculate = s3c2410_nand_calculate_ecc;
        nand->ecc.correct = s3c2410_nand_correct_data;
-       nand->ecc.mode = NAND_ECC_HW3_512;
+       nand->ecc.mode = NAND_ECC_HW;
+       nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
+       nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+       nand->ecc.strength = 1;
 #else
        nand->ecc.mode = NAND_ECC_SOFT;
 #endif
 
 #ifdef CONFIG_S3C2410_NAND_BBT
-       nand->options = NAND_USE_FLASH_BBT;
-#else
-       nand->options = 0;
+       nand->bbt_options |= NAND_BBT_USE_FLASH;
 #endif
 
-       debugX(1, "end of nand_init\n");
+       debug("end of nand_init\n");
 
        return 0;
 }