*/
#define FEC_XFER_TIMEOUT 5000
+/*
+ * The standard 32-byte DMA alignment does not work on mx6solox, which requires
+ * 64-byte alignment in the DMA RX FEC buffer.
+ * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
+ * satisfies the alignment on other SoCs (32-bytes)
+ */
+#define FEC_DMA_RX_MINALIGN 64
+
#ifndef CONFIG_MII
#error "CONFIG_MII has to be defined!"
#endif
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
- writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
- ð->mii_speed);
+ register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000);
+#ifdef FEC_QUIRK_ENET_MAC
+ speed--;
+#endif
+ speed <<= 1;
+ writel(speed, ð->mii_speed);
debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
}
* @param[in] dsize desired size of each receive buffer
* @return 0 on success
*
- * For this task we need additional memory for the data buffers. And each
- * data buffer requires some alignment. Thy must be aligned to a specific
- * boundary each.
+ * Init all RX descriptors to default values.
*/
-static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
+static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
{
uint32_t size;
+ uint8_t *data;
int i;
/*
- * Allocate memory for the buffers. This allocation respects the
- * alignment
+ * Reload the RX descriptors with default values and wipe
+ * the RX buffers.
*/
size = roundup(dsize, ARCH_DMA_MINALIGN);
for (i = 0; i < count; i++) {
- uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
- if (data_ptr == 0) {
- uint8_t *data = memalign(ARCH_DMA_MINALIGN,
- size);
- if (!data) {
- printf("%s: error allocating rxbuf %d\n",
- __func__, i);
- goto err;
- }
- writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
- } /* needs allocation */
- writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
- writew(0, &fec->rbd_base[i].data_length);
+ data = (uint8_t *)fec->rbd_base[i].data_pointer;
+ memset(data, 0, dsize);
+ flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+
+ fec->rbd_base[i].status = FEC_RBD_EMPTY;
+ fec->rbd_base[i].data_length = 0;
}
/* Mark the last RBD to close the ring. */
- writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
+ fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
fec->rbd_index = 0;
- return 0;
-
-err:
- for (; i >= 0; i--) {
- uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
- free((void *)data_ptr);
- }
-
- return -ENOMEM;
+ flush_dcache_range((unsigned)fec->rbd_base,
+ (unsigned)fec->rbd_base + size);
}
/**
unsigned addr = (unsigned)fec->tbd_base;
unsigned size = roundup(2 * sizeof(struct fec_bd),
ARCH_DMA_MINALIGN);
- writew(0x0000, &fec->tbd_base[0].status);
- writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
+
+ memset(fec->tbd_base, 0, size);
+ fec->tbd_base[0].status = 0;
+ fec->tbd_base[1].status = FEC_TBD_WRAP;
fec->tbd_index = 0;
- flush_dcache_range(addr, addr+size);
+ flush_dcache_range(addr, addr + size);
}
/**
*/
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
&fec->eth->ecntrl);
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
udelay(100);
/*
* setup the MII gasket for RMII mode
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
- uint32_t size;
- int i, ret;
+ int i;
/* Initialize MAC address */
fec_set_hwaddr(dev);
/*
- * Allocate transmit descriptors, there are two in total. This
- * allocation respects cache alignment.
+ * Setup transmit descriptors, there are two in total.
*/
- if (!fec->tbd_base) {
- size = roundup(2 * sizeof(struct fec_bd),
- ARCH_DMA_MINALIGN);
- fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
- if (!fec->tbd_base) {
- ret = -ENOMEM;
- goto err1;
- }
- memset(fec->tbd_base, 0, size);
- fec_tbd_init(fec);
- }
+ fec_tbd_init(fec);
- /*
- * Allocate receive descriptors. This allocation respects cache
- * alignment.
- */
- if (!fec->rbd_base) {
- size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
- ARCH_DMA_MINALIGN);
- fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
- if (!fec->rbd_base) {
- ret = -ENOMEM;
- goto err2;
- }
- memset(fec->rbd_base, 0, size);
- /*
- * Initialize RxBD ring
- */
- if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
- ret = -ENOMEM;
- goto err3;
- }
- flush_dcache_range((unsigned)fec->rbd_base,
- (unsigned)fec->rbd_base + size);
- }
+ /* Setup receive descriptors. */
+ fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
fec_reg_setup(fec);
#endif
fec_open(dev);
return 0;
-
-err3:
- free(fec->rbd_base);
-err2:
- free(fec->tbd_base);
-err1:
- return ret;
}
/**
break;
}
- if (!timeout)
+ if (!timeout) {
ret = -EINVAL;
+ goto out;
+ }
- invalidate_dcache_range(addr, addr + size);
- if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
+ /*
+ * The TDAR bit is cleared when the descriptors are all out from TX
+ * but on mx6solox we noticed that the READY bit is still not cleared
+ * right after TDAR.
+ * These are two distinct signals, and in IC simulation, we found that
+ * TDAR always gets cleared prior than the READY bit of last BD becomes
+ * cleared.
+ * In mx6solox, we use a later version of FEC IP. It looks like that
+ * this intrinsic behaviour of TDAR bit has changed in this newer FEC
+ * version.
+ *
+ * Fix this by polling the READY bit of BD after the TDAR polling,
+ * which covers the mx6solox case and does not harm the other SoCs.
+ */
+ timeout = FEC_XFER_TIMEOUT;
+ while (--timeout) {
+ invalidate_dcache_range(addr, addr + size);
+ if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
+ FEC_TBD_READY))
+ break;
+ }
+
+ if (!timeout)
ret = -EINVAL;
+out:
debug("fec_send: status 0x%x index %d ret %i\n",
readw(&fec->tbd_base[fec->tbd_index].status),
fec->tbd_index, ret);
uint16_t bd_status;
uint32_t addr, size, end;
int i;
- uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN);
+ ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
/*
* Check if any critical events have happened
sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
}
+static int fec_alloc_descs(struct fec_priv *fec)
+{
+ unsigned int size;
+ int i;
+ uint8_t *data;
+
+ /* Allocate TX descriptors. */
+ size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
+ fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
+ if (!fec->tbd_base)
+ goto err_tx;
+
+ /* Allocate RX descriptors. */
+ size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
+ fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
+ if (!fec->rbd_base)
+ goto err_rx;
+
+ memset(fec->rbd_base, 0, size);
+
+ /* Allocate RX buffers. */
+
+ /* Maximum RX buffer size. */
+ size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
+ for (i = 0; i < FEC_RBD_NUM; i++) {
+ data = memalign(FEC_DMA_RX_MINALIGN, size);
+ if (!data) {
+ printf("%s: error allocating rxbuf %d\n", __func__, i);
+ goto err_ring;
+ }
+
+ memset(data, 0, size);
+
+ fec->rbd_base[i].data_pointer = (uint32_t)data;
+ fec->rbd_base[i].status = FEC_RBD_EMPTY;
+ fec->rbd_base[i].data_length = 0;
+ /* Flush the buffer to memory. */
+ flush_dcache_range((uint32_t)data, (uint32_t)data + size);
+ }
+
+ /* Mark the last RBD to close the ring. */
+ fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
+
+ fec->rbd_index = 0;
+ fec->tbd_index = 0;
+
+ return 0;
+
+err_ring:
+ for (; i >= 0; i--)
+ free((void *)fec->rbd_base[i].data_pointer);
+ free(fec->rbd_base);
+err_rx:
+ free(fec->tbd_base);
+err_tx:
+ return -ENOMEM;
+}
+
+static void fec_free_descs(struct fec_priv *fec)
+{
+ int i;
+
+ for (i = 0; i < FEC_RBD_NUM; i++)
+ free((void *)fec->rbd_base[i].data_pointer);
+ free(fec->rbd_base);
+ free(fec->tbd_base);
+}
+
#ifdef CONFIG_PHYLIB
int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
struct mii_dev *bus, struct phy_device *phydev)
memset(edev, 0, sizeof(*edev));
memset(fec, 0, sizeof(*fec));
+ ret = fec_alloc_descs(fec);
+ if (ret)
+ goto err3;
+
edev->priv = fec;
edev->init = fec_init;
edev->send = fec_send;
while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
printf("FEC MXC: Timeout reseting chip\n");
- goto err3;
+ goto err4;
}
udelay(10);
}
if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
+ if (!getenv("ethaddr"))
+ eth_setenv_enetaddr("ethaddr", ethaddr);
}
return ret;
+err4:
+ fec_free_descs(fec);
err3:
free(fec);
err2:
projects / karo-tx-uboot.git / blobdiff