/*
- * (C) Copyright 2003-2005
+ * (C) Copyright 2003-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This file is based on mpc4200fec.c,
#include <mpc5xxx_sdma.h>
#include <malloc.h>
#include <net.h>
+#include <netdev.h>
#include <miiphy.h>
#include "mpc5xxx_fec.h"
/* #define DEBUG 0x28 */
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
- defined(CONFIG_MPC5xxx_FEC)
-
#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
#endif /* DEBUG */
-#if (DEBUG & 0x40)
-static uint32 local_crc32(char *string, unsigned int crc_value, int len);
-#endif
-
typedef struct {
uint8 data[1500]; /* actual data */
int length; /* actual length */
uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
} NBUF;
-int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
-int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
+int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 *retVal);
+int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
+
+static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis);
/********************************************************************/
#if (DEBUG & 0x2)
printf ("mpc5xxx_fec_init... Begin\n");
#endif
+ mpc5xxx_fec_init_phy(dev, bis);
+
+ /*
+ * Call board-specific PHY fixups (if any)
+ */
+#ifdef CONFIG_RESET_PHY_R
+ reset_phy();
+#endif
+
/*
* Initialize RxBD/TxBD rings
*/
}
fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
- if (fec->xcv_type != SEVENWIRE) {
- /*
- * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
- * and do not drop the Preamble.
- */
- fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
- }
/*
* Set Opcode/Pause Duration Register
*/
fec->eth->xmit_fsm = 0x03000000;
-#if defined(CONFIG_MPC5200)
/*
- * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
+ * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
* work w/ the current receive task.
*/
sdma->PtdCntrl |= 0x00000001;
-#endif
/*
* Set priority of different initiators
{
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
+ static int initialized = 0;
+
+ if(initialized)
+ return 0;
+ initialized = 1;
#if (DEBUG & 0x1)
printf ("mpc5xxx_fec_init_phy... Begin\n");
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
+ * No MII for 7-wire mode
*/
- fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
+ fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
}
if (fec->xcv_type != SEVENWIRE) {
/********************************************************************/
static void mpc5xxx_fec_halt(struct eth_device *dev)
{
-#if defined(CONFIG_MPC5200)
struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
-#endif
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
int counter = 0xffff;
SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
-#if defined(CONFIG_MPC5200)
/*
- * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
+ * Turn on COMM bus prefetch in the MPC5200 BestComm after we're
* done. It doesn't work w/ the current receive task.
*/
sdma->PtdCntrl &= ~0x00000001;
-#endif
/*
* Disable the Ethernet Controller
*/
udelay(10);
+ /* don't leave the MII speed set to zero */
+ if (fec->xcv_type != SEVENWIRE) {
+ /*
+ * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
+ * and do not drop the Preamble.
+ * No MII for 7-wire mode
+ */
+ fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
+ }
+
#if (DEBUG & 0x3)
printf("Ethernet task stopped\n");
#endif
/********************************************************************/
-static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
+static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
int data_length)
{
/*
fec->eth = (ethernet_regs *)MPC5XXX_FEC;
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
-#if defined(CONFIG_CANMB) || \
- defined(CONFIG_CM5200) || \
- defined(CONFIG_HMI1001) || \
- defined(CONFIG_ICECUBE) || \
- defined(CONFIG_INKA4X0) || \
- defined(CONFIG_JUPITER) || \
- defined(CONFIG_MCC200) || \
- defined(CONFIG_MOTIONPRO) || \
- defined(CONFIG_MUCMC52) || \
- defined(CONFIG_O2DNT) || \
- defined(CONFIG_PM520) || \
- defined(CONFIG_TOP5200) || \
- defined(CONFIG_TQM5200) || \
- defined(CONFIG_UC101) || \
- defined(CONFIG_V38B) || \
- defined(CONFIG_MUNICES)
-# ifndef CONFIG_FEC_10MBIT
+#if defined(CONFIG_MPC5xxx_FEC_MII100)
fec->xcv_type = MII100;
-# else
+#elif defined(CONFIG_MPC5xxx_FEC_MII10)
fec->xcv_type = MII10;
-# endif
-#elif defined(CONFIG_TOTAL5200)
+#elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
fec->xcv_type = SEVENWIRE;
#else
#error fec->xcv_type not initialized.
#endif
+ if (fec->xcv_type != SEVENWIRE) {
+ /*
+ * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
+ * and do not drop the Preamble.
+ * No MII for 7-wire mode
+ */
+ fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
+ }
dev->priv = (void *)fec;
dev->iobase = MPC5XXX_FEC;
dev->send = mpc5xxx_fec_send;
dev->recv = mpc5xxx_fec_recv;
- sprintf(dev->name, "FEC ETHERNET");
+ sprintf(dev->name, "FEC");
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
}
- mpc5xxx_fec_init_phy(dev, bis);
-
return 1;
}
/* MII-interface related functions */
/********************************************************************/
-int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
+int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
{
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
uint32 reg; /* convenient holder for the PHY register */
}
/********************************************************************/
-int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
+int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
{
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
uint32 reg; /* convenient holder for the PHY register */
return 0;
}
-
-#if (DEBUG & 0x40)
-static uint32 local_crc32(char *string, unsigned int crc_value, int len)
-{
- int i;
- char c;
- unsigned int crc, count;
-
- /*
- * crc32 algorithm
- */
- /*
- * crc = 0xffffffff; * The initialized value should be 0xffffffff
- */
- crc = crc_value;
-
- for (i = len; --i >= 0;) {
- c = *string++;
- for (count = 0; count < 8; count++) {
- if ((c & 0x01) ^ (crc & 0x01)) {
- crc >>= 1;
- crc = crc ^ 0xedb88320;
- } else {
- crc >>= 1;
- }
- c >>= 1;
- }
- }
-
- /*
- * In big endian system, do byte swaping for crc value
- */
- /**/ return crc;
-}
-#endif /* DEBUG */
-
-#endif /* CONFIG_MPC5xxx_FEC */
projects / karo-tx-uboot.git / blobdiff