net: sh-eth: Add support R8A7790

[karo-tx-uboot.git] / drivers / net / sh_eth.h

diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 568fafe5f51fc4318ce1a3c3976e3a72e54c34fe..43b8ac9ce80c9f26c7329952ac74f730d6474b2b 100644 (file)
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -5,19 +5,7 @@
  * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
  *
- * This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <netdev.h>
@@ -43,6 +31,11 @@
 #define ADDR_TO_P2(addr)       (addr)
 #endif /* defined(CONFIG_SH) */
 
+/* base padding size is 16 */
+#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
+#endif
+
 /* Number of supported ports */
 #define MAX_PORT_NUM   2
 
@@ -57,15 +50,16 @@
 
 /* The size of the tx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
-#define TX_DESC_PADDING                4
-#define TX_DESC_SIZE           (12 + TX_DESC_PADDING)
+#define TX_DESC_PADDING        (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
+#define TX_DESC_SIZE   (12 + TX_DESC_PADDING)
 
 /* Tx descriptor. We always use 3 bytes of padding */
 struct tx_desc_s {
        volatile u32 td0;
        u32 td1;
        u32 td2;                /* Buffer start */
-       u32 padding;
+       u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
 };
 
 /* There is no limitation in the number of rx descriptors */
@@ -73,15 +67,18 @@ struct tx_desc_s {
 
 /* The size of the rx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
-#define RX_DESC_PADDING                4
+#define RX_DESC_PADDING        (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
 #define RX_DESC_SIZE           (12 + RX_DESC_PADDING)
+/* aligned cache line size */
+#define RX_BUF_ALIGNE_SIZE     (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
 
 /* Rx descriptor. We always use 4 bytes of padding */
 struct rx_desc_s {
        volatile u32 rd0;
        volatile u32 rd1;
        u32 rd2;                /* Buffer start */
-       u32 padding;
+       u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
 };
 
 struct sh_eth_info {
@@ -169,6 +166,7 @@ enum {
        TLFRCR,
        CERCR,
        CEECR,
+       RMIIMR, /* R8A7790 */
        MAFCR,
        RTRATE,
        CSMR,
@@ -275,6 +273,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
        [RMCR]  = 0x0058,
        [TFUCR] = 0x0064,
        [RFOCR] = 0x0068,
+       [RMIIMR] = 0x006C,
        [FCFTR] = 0x0070,
        [RPADIR]        = 0x0078,
        [TRIMD] = 0x007c,
@@ -302,6 +301,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #elif defined(CONFIG_R8A7740)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR   0xE9A00000
+#elif defined(CONFIG_R8A7790)
+#define SH_ETH_TYPE_ETHER
+#define BASE_IO_ADDR   0xEE700200
 #endif
 
 /*
@@ -332,6 +334,14 @@ enum DMAC_M_BIT {
 #endif
 };
 
+#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
+# define EMDR_DESC EDMR_DL1
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
+# define EMDR_DESC EDMR_DL0
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
+# define EMDR_DESC 0
+#endif
+
 /* RFLR */
 #define RFLR_RFL_MIN   0x05EE  /* Recv Frame length 1518 byte */
 
@@ -497,6 +507,8 @@ enum FELIC_MODE_BIT {
        ECMR_PRM = 0x00000001,
 #ifdef CONFIG_CPU_SH7724
        ECMR_RTM = 0x00000010,
+#elif defined(CONFIG_R8A7790)
+       ECMR_RTM = 0x00000004,
 #endif
 
 };