karo: merge with Ka-Ro specific tree for secure boot support

[karo-tx-uboot.git] / drivers / usb / host / ehci-mx6.c

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index c0a557b2adc9c893e3ea7d02557c5152e1fd79e1..154be8cb7cbe1e01c31f9f18c917205546712c22 100644 (file)
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -40,10 +40,10 @@
 #define ANADIG_USB2_CHRG_DETECT_EN_B           0x00100000
 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B     0x00080000
 
-#define ANADIG_USB2_PLL_480_CTRL_BYPASS                0x00010000
-#define ANADIG_USB2_PLL_480_CTRL_ENABLE                0x00002000
-#define ANADIG_USB2_PLL_480_CTRL_POWER         0x00001000
-#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS   0x00000040
+#define ANADIG_USB_PLL_480_CTRL_BYPASS         0x00010000
+#define ANADIG_USB_PLL_480_CTRL_ENABLE         0x00002000
+#define ANADIG_USB_PLL_480_CTRL_POWER          0x00001000
+#define ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS    0x00000040
 
 
 #define UCTRL_OVER_CUR_POL     (1 << 8) /* OTG Polarity of Overcurrent */
@@ -104,12 +104,12 @@ static void usb_power_config(int index)
                     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
                     chrg_detect);
 
-       __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
+       __raw_writel(ANADIG_USB_PLL_480_CTRL_BYPASS,
                     pll_480_ctrl_clr);
 
-       __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
-                    ANADIG_USB2_PLL_480_CTRL_POWER |
-                    ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
+       __raw_writel(ANADIG_USB_PLL_480_CTRL_ENABLE |
+                    ANADIG_USB_PLL_480_CTRL_POWER |
+                    ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS,
                     pll_480_ctrl_set);
 }
 
@@ -160,7 +160,7 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci)
        val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
        __raw_writel(val, phy_ctrl);
 
-       return val & USBPHY_CTRL_OTG_ID;
+       return 0;
 }
 
 /* Base address for this IP block is 0x02184800 */
@@ -174,7 +174,7 @@ struct usbnc_regs {
 
 static void usb_oc_config(int index)
 {
-       struct usbnc_regs *usbnc = (struct usbnc_regs *)(USBOH3_USB_BASE_ADDR +
+       struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
                        USB_OTHERREGS_OFFSET);
        void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
        u32 val;
@@ -193,6 +193,28 @@ static void usb_oc_config(int index)
        __raw_writel(val, ctrl);
 }
 
+int usb_phy_mode(int port)
+{
+       void __iomem *phy_reg;
+       void __iomem *phy_ctrl;
+       u32 val;
+
+       phy_reg = (void __iomem *)phy_bases[port];
+       phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+       val = __raw_readl(phy_ctrl);
+
+       if (val & USBPHY_CTRL_OTG_ID)
+               return USB_INIT_DEVICE;
+       else
+               return USB_INIT_HOST;
+}
+
+int __weak board_usb_phy_mode(int port)
+{
+       return usb_phy_mode(port);
+}
+
 int __weak board_ehci_hcd_init(int port)
 {
        return 0;
@@ -207,7 +229,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
                struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
        enum usb_init_type type;
-       struct usb_ehci *ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
+       struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
                (0x200 * index));
 
        if (index > 3)
@@ -221,7 +243,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
        usb_power_config(index);
        usb_oc_config(index);
        usb_internal_phy_clock_gate(index, 1);
-       type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+       usb_phy_enable(index, ehci);
+       type = board_usb_phy_mode(index);
 
        *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
        *hcor = (struct ehci_hcor *)((uint32_t)*hccr +