Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / drivers / video / ipu_regs.h

diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index 9964c2039c966d0048ea83a22d44235bca318946..982e25250970c45db57eeec2f82f55d70dc3e182 100644 (file)
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -33,28 +33,38 @@
 #define IPU_DISP0_BASE         0x00000000
 #define IPU_MCU_T_DEFAULT      8
 #define IPU_DISP1_BASE         (IPU_MCU_T_DEFAULT << 25)
-#define IPU_CM_REG_BASE                0x1E000000
-#define IPU_STAT_REG_BASE      0x1E000200
-#define IPU_IDMAC_REG_BASE     0x1E008000
-#define IPU_ISP_REG_BASE       0x1E010000
-#define IPU_DP_REG_BASE                0x1E018000
-#define IPU_IC_REG_BASE                0x1E020000
-#define IPU_IRT_REG_BASE       0x1E028000
-#define IPU_CSI0_REG_BASE      0x1E030000
-#define IPU_CSI1_REG_BASE      0x1E038000
-#define IPU_DI0_REG_BASE       0x1E040000
-#define IPU_DI1_REG_BASE       0x1E048000
-#define IPU_SMFC_REG_BASE      0x1E050000
-#define IPU_DC_REG_BASE                0x1E058000
-#define IPU_DMFC_REG_BASE      0x1E060000
-#define IPU_CPMEM_REG_BASE     0x1F000000
-#define IPU_LUT_REG_BASE       0x1F020000
-#define IPU_SRM_REG_BASE       0x1F040000
-#define IPU_TPM_REG_BASE       0x1F060000
-#define IPU_DC_TMPL_REG_BASE   0x1F080000
-#define IPU_ISP_TBPR_REG_BASE  0x1F0C0000
-#define IPU_VDI_REG_BASE       0x1E068000
+#define IPU_CM_REG_BASE                0x00000000
+#define IPU_STAT_REG_BASE      0x00000200
+#define IPU_IDMAC_REG_BASE     0x00008000
+#define IPU_ISP_REG_BASE       0x00010000
+#define IPU_DP_REG_BASE                0x00018000
+#define IPU_IC_REG_BASE                0x00020000
+#define IPU_IRT_REG_BASE       0x00028000
+#define IPU_CSI0_REG_BASE      0x00030000
+#define IPU_CSI1_REG_BASE      0x00038000
+#define IPU_DI0_REG_BASE       0x00040000
+#define IPU_DI1_REG_BASE       0x00048000
+#define IPU_SMFC_REG_BASE      0x00050000
+#define IPU_DC_REG_BASE                0x00058000
+#define IPU_DMFC_REG_BASE      0x00060000
+#define IPU_VDI_REG_BASE       0x00680000
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#define IPU_CPMEM_REG_BASE     0x01000000
+#define IPU_LUT_REG_BASE       0x01020000
+#define IPU_SRM_REG_BASE       0x01040000
+#define IPU_TPM_REG_BASE       0x01060000
+#define IPU_DC_TMPL_REG_BASE   0x01080000
+#define IPU_ISP_TBPR_REG_BASE  0x010C0000
+#elif defined(CONFIG_MX6)
+#define IPU_CPMEM_REG_BASE     0x00100000
+#define IPU_LUT_REG_BASE       0x00120000
+#define IPU_SRM_REG_BASE       0x00140000
+#define IPU_TPM_REG_BASE       0x00160000
+#define IPU_DC_TMPL_REG_BASE   0x00180000
+#define IPU_ISP_TBPR_REG_BASE  0x001C0000
+#endif
 
+#define IPU_CTRL_BASE_ADDR     (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
 
 extern u32 *ipu_dc_tmpl_reg;