mpc83xx: bump loadaddr over fdtaddr to 0x500000

[karo-tx-uboot.git] / include / configs / MPC8349ITX.h

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 58ee13d3f37b0c7d1b6574b788fe59a02c6e7dd4..be8850a7e702fd3c3a9c878f21ce430d073ff302 100644 (file)
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -68,12 +68,16 @@
 
 #define CFG_IMMR               0xE0000000      /* The IMMR is relocated to here */
 
+#define CONFIG_MISC_INIT_F
+#define CONFIG_MISC_INIT_R
 
-/* On-board devices */
+/*
+ * On-board devices
+ */
 
 #ifdef CONFIG_MPC8349ITX
 #define CONFIG_COMPACT_FLASH   /* The CF card interface on the back of the board */
-#define CONFIG_VSC7385         /* The Vitesse 7385 5-port switch */
+#define CONFIG_VSC7385_ENET    /* VSC7385 ethernet support */
 #endif
 
 #define CONFIG_PCI
@@ -88,9 +92,6 @@
 /* I2C */
 #ifdef CONFIG_HARD_I2C
 
-#define CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
@@ -155,7 +156,7 @@
 #define CFG_MEMTEST_END                0x2000
 
 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
-                               DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+                               DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 
 #ifdef CONFIG_HARD_I2C
 #define CONFIG_SPD_EEPROM              /* use SPD EEPROM for DDR setup*/
@@ -190,6 +191,18 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_FLASH_SIZE         16              /* FLASH size in MB */
 #define CFG_FLASH_SIZE_SHIFT   4               /* log2 of the above value */
 
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE           0xFEFFE000
+#define CONFIG_VSC7385_IMAGE_SIZE      8192
+
+#endif
+
 /*
  * BRx, ORx, LBLAWBARx, and LBLAWARx
  */
@@ -205,10 +218,10 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 /* Vitesse 7385 */
 
-#ifdef CONFIG_VSC7385
-
 #define CFG_VSC7385_BASE       0xF8000000
 
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR1_PRELIM         (CFG_VSC7385_BASE | BR_PS_8 | BR_V)
 #define CFG_OR1_PRELIM         (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
                                OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
@@ -261,6 +274,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
 
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
 #define CFG_MONITOR_LEN                (256 * 1024) /* Reserve 256 kB for Mon */
 #define CFG_MALLOC_LEN         (128 * 1024) /* Reserved for malloc */
 
@@ -296,16 +310,9 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_NS16550_COM2       (CFG_IMMR + 0x4600)
 
 /* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE
-#define CONFIG_OF_BOARD_SETUP
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE  8192
-
-#define OF_CPU                 "PowerPC,8349@0"
-#define OF_SOC                 "soc8349@e0000000"
-#define OF_TBCLK               (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH         "/soc8349@e0000000/serial@4500"
+#define CONFIG_OF_LIBFDT       1
+#define CONFIG_OF_BOARD_SETUP  1
+#define CONFIG_OF_STDOUT_VIA_ALIAS     1
 
 /*
  * PCI
@@ -378,6 +385,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_TSEC1
 
 #ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME  "TSEC0"
 #define CFG_TSEC1_OFFSET       0x24000
 #define TSEC1_PHY_ADDR         0x1c    /* VSC8201 uses address 0x1c */
@@ -389,7 +397,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME  "TSEC1"
 #define CFG_TSEC2_OFFSET       0x25000
-#define CONFIG_UNKNOWN_TSEC    /* TSEC2 is proprietary */
+
 #define TSEC2_PHY_ADDR         4
 #define TSEC2_PHYIDX           0
 #define TSEC2_FLAGS            TSEC_GIGABIT
@@ -406,8 +414,8 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 #ifndef CFG_RAMBOOT
   #define CFG_ENV_IS_IN_FLASH
+  #define CFG_ENV_ADDR         (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
   #define CFG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) for environment */
-  #define CFG_ENV_ADDR         (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE))
   #define CFG_ENV_SIZE         0x2000
 #else
   #define CFG_NO_FLASH         /* Flash is not usable now */
@@ -466,7 +474,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_PROMPT_HUSH_PS2 "> "
 
 #define CFG_LOAD_ADDR  0x2000000       /* default load address */
-#define CONFIG_LOADADDR        200000  /* default location for tftp and bootm */
+#define CONFIG_LOADADDR        500000  /* default location for tftp and bootm */
 
 #ifdef CONFIG_MPC8349ITX
 #define CFG_PROMPT     "MPC8349E-mITX> "       /* Monitor Command Prompt */
@@ -492,15 +500,6 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CFG_BOOTMAPSZ  (8 << 20)       /* Initial Memory map for Linux*/
 
-/*
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE                32768
-#define CFG_CACHELINE_SIZE     32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5       /* log2 of the above value */
-#endif
-
 #define CFG_HRCW_LOW (\
        HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
        HRCWL_DDR_TO_SCB_CLK_1X1 |\
@@ -633,11 +632,11 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_TSEC1
+#ifdef CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR         00:E0:0C:00:8C:01
 #endif
 
-#ifdef CONFIG_TSEC2
+#ifdef CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR                00:E0:0C:00:8C:02
 #endif