Unified codebase for TX28, TX48, TX51, TX53

[karo-tx-uboot.git] / include / configs / devkit8000.h

diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index e1743dc5eeb766202942849159e8fc868d4a3bbf..248a5b2fa36c3d5a1d2cbda9d21bc6af1e80ef15 100644 (file)
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -34,10 +34,15 @@
 /* High Level Configuration Options */
 #define CONFIG_OMAP            1       /* in a TI OMAP core */
 #define CONFIG_OMAP34XX                1       /* which is a 34XX */
-#define CONFIG_OMAP3430                1       /* which is in a 3430 */
 #define CONFIG_OMAP3_DEVKIT8000        1       /* working with DevKit8000 */
-
-#define        CONFIG_SYS_TEXT_BASE    0x80008000
+#define CONFIG_MACH_TYPE       MACH_TYPE_DEVKIT8000
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE   0x80100000
 
 #define CONFIG_SDRC    /* The chip has SDRC controller */
 
@@ -68,10 +73,6 @@
 #define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + (128 << 10))
 
 /* Hardware drivers */
-
-/* DDR - I use Micron DDR */
-#define CONFIG_OMAP3_MICRON_DDR                1
-
 /* DM9000 */
 #define CONFIG_NET_RETRY_COUNT         20
 #define        CONFIG_DRIVER_DM9000            1
@@ -276,20 +277,12 @@
 
 /* The stack sizes are set up in start.S using the settings below */
 #define CONFIG_STACKSIZE       (128 << 10)     /* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ           (4 << 10)       /* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ           (4 << 10)       /* FIQ stack 4 KiB */
-#endif
 
 /*  Physical Memory Map  */
 #define CONFIG_NR_DRAM_BANKS           2 /* CS1 may or may not be populated */
 #define PHYS_SDRAM_1                   OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE              (128 << 20)     /* at least 128 MiB */
 #define PHYS_SDRAM_2                   OMAP34XX_SDRC_CS1
 
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C                     1
-
 /* NAND and environment organization  */
 #define PISMO1_NAND_SIZE               GPMC_SIZE_128M
 
@@ -317,6 +310,7 @@
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_I2C_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
@@ -330,10 +324,10 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 
 #define CONFIG_SPL_TEXT_BASE           0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE            0xB400  /* 45 K */
+#define CONFIG_SPL_MAX_SIZE            (54 * 1024)     /* 8 KB for stack */
 #define CONFIG_SPL_STACK               LOW_LEVEL_SRAM_STACK
 
-#define CONFIG_SPL_BSS_START_ADDR      0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
+#define CONFIG_SPL_BSS_START_ADDR       0x80000500 /* leave space for bootargs*/
 #define CONFIG_SPL_BSS_MAX_SIZE                0x80000
 
 /* NAND boot config */
@@ -349,17 +343,23 @@
 #define CONFIG_SYS_NAND_ECCSIZE                512
 #define CONFIG_SYS_NAND_ECCBYTES       3
 
-#define CONFIG_SYS_NAND_ECCSTEPS       (CONFIG_SYS_NAND_PAGE_SIZE / \
-                                               CONFIG_SYS_NAND_ECCSIZE)
-#define CONFIG_SYS_NAND_ECCTOTAL       (CONFIG_SYS_NAND_ECCBYTES * \
-                                               CONFIG_SYS_NAND_ECCSTEPS)
-
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x80000
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    0x200000
 
-#define CONFIG_SYS_SPL_MALLOC_START    0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START    0x80208000
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000        /* 1 MB */
 
+/* SPL OS boot options */
+#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_OS_BOOT_KEY 26
+
+#define CONFIG_CMD_SPL
+#define CONFIG_CMD_SPL_WRITE_SIZE       0x400 /* 1024 byte */
+#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
+                                       0x400000)
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_SYS_SPL_ARGS_ADDR        (PHYS_SDRAM_1 + 0x100)
+
 #endif /* __CONFIG_H */