#endif
#include <net.h>
#ifdef CFG_ALLOC_DPRAM
-#if !defined(CONFIG_8260)
+#if !(defined(CONFIG_8260)||defined(CONFIG_MPC8560))
#include <commproc.h>
#endif
#endif
#if defined(CONFIG_LOGBUFFER)
#include <logbuff.h>
#endif
+#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500)
+#include <asm/cache.h>
+#endif
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
void doc_init (void);
get_clocks, /* get CPU and bus clocks (etc.) */
init_timebase,
#ifdef CFG_ALLOC_DPRAM
-#if !defined(CONFIG_8260)
+#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
dpram_init,
#endif
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
-#ifndef CONFIG_8260
+#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
#endif
bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */
#endif
-#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx)
+#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
+ defined(CONFIG_E500)
bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5XXX)
WATCHDOG_RESET ();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
bd->bi_cpmfreq = gd->cpm_clk;
bd->bi_brgfreq = gd->brg_clk;
bd->bi_sccfreq = gd->scc_clk;
icache_enable (); /* it's time to enable the instruction cache */
#endif
+#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500)
+ unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
+#endif
+
#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45)
/*
* Do PCI configuration on BAB7xx and CPC45 _before_ the flash
load_sernum_ethaddr ();
#endif
-#if defined(CFG_GT_6426x) || defined(CONFIG_PN62) || defined(CONFIG_PPCHAMELEONEVB)
+#if defined(CFG_GT_6426x) || defined(CONFIG_PN62) || defined(CONFIG_PPCHAMELEONEVB) || \
+ defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
/* handle the 2nd ethernet address */
s = getenv ("eth1addr");
s = (*e) ? e + 1 : e;
}
#endif
-#if defined(CFG_GT_6426x)
+#if defined(CFG_GT_6426x) || defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
/* handle the 3rd ethernet address */
s = getenv ("eth2addr");
defined(CONFIG_LWMON) || \
defined(CONFIG_MPC8260ADS) || \
defined(CONFIG_MPC8266ADS) || \
+ defined(CONFIG_MPC8560ADS) || \
defined(CONFIG_PCU_E) || \
defined(CONFIG_RPXSUPER) || \
defined(CONFIG_SPD823TS) )
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
WATCHDOG_RESET ();
+ puts ("NAND:");
nand_init(); /* go init the NAND */
#endif