imported Ka-Ro specific additions to U-Boot 2009.08 for TX28

[karo-tx-uboot.git] / lib_ppc / cache.c

diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c
index a81ab5e363f013edab4a84e470927a51f3af88a4..338b08bd77005f0b477ad594ce1c37d588943bf2 100755 (executable)
--- a/lib_ppc/cache.c
+++ b/lib_ppc/cache.c
@@ -22,29 +22,32 @@
  */
 
 #include <common.h>
+#include <asm/cache.h>
+#include <watchdog.h>
 
-
-void flush_cache (ulong start_addr, ulong size)
+void flush_cache(ulong start_addr, ulong size)
 {
 #ifndef CONFIG_5xx
-       ulong addr, end_addr = start_addr + size;
+       ulong addr, start, end;
+
+       start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+       end = start_addr + size - 1;
 
-       if (CFG_CACHELINE_SIZE) {
-               addr = start_addr & (CFG_CACHELINE_SIZE - 1);
-               for (addr = start_addr;
-                    addr < end_addr;
-                    addr += CFG_CACHELINE_SIZE) {
-                       asm ("dcbst 0,%0": :"r" (addr));
-               }
-               asm ("sync");   /* Wait for all dcbst to complete on bus */
+       for (addr = start; (addr <= end) && (addr >= start);
+                       addr += CONFIG_SYS_CACHELINE_SIZE) {
+               asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
+               WATCHDOG_RESET();
+       }
+       /* wait for all dcbst to complete on bus */
+       asm volatile("sync" : : : "memory");
 
-               for (addr = start_addr;
-                    addr < end_addr;
-                    addr += CFG_CACHELINE_SIZE) {
-                       asm ("icbi 0,%0": :"r" (addr));
-               }
+       for (addr = start; (addr <= end) && (addr >= start);
+                       addr += CONFIG_SYS_CACHELINE_SIZE) {
+               asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
+               WATCHDOG_RESET();
        }
-       asm ("sync");           /* Always flush prefetch queue in any case */
-       asm ("isync");
+       asm volatile("sync" : : : "memory");
+       /* flush prefetch queue */
+       asm volatile("isync" : : : "memory");
 #endif
 }