/*
- * (C) Copyright 2006-2007
+ * (C) Copyright 2006-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
#include <common.h>
#include <nand.h>
+#include <asm/io.h>
#define CFG_NAND_READ_DELAY \
{ volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
extern void board_nand_init(struct nand_chip *nand);
+#if (CFG_NAND_PAGE_SIZE <= 512)
+/*
+ * NAND command for small page NAND devices (512)
+ */
+static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
+{
+ struct nand_chip *this = mtd->priv;
+ int page_addr = page + block * CFG_NAND_PAGE_COUNT;
+ int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
+
+ if (this->dev_ready)
+ while (!this->dev_ready(mtd))
+ ;
+ else
+ CFG_NAND_READ_DELAY;
+
+ /* Begin command latch cycle */
+ this->cmd_ctrl(mtd, cmd, ctrl);
+ /* Set ALE and clear CLE to start address cycle */
+ ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
+ /* Column address */
+ this->cmd_ctrl(mtd, offs, ctrl);
+ ctrl &= ~NAND_CTRL_CHANGE;
+ this->cmd_ctrl(mtd, (u8)(page_addr & 0xff), ctrl); /* A[16:9] */
+ ctrl &= ~NAND_CTRL_CHANGE;
+ this->cmd_ctrl(mtd, (u8)((page_addr >> 8) & 0xff), ctrl); /* A[24:17] */
+#ifdef CFG_NAND_4_ADDR_CYCLE
+ /* One more address cycle for devices > 32MiB */
+ this->cmd_ctrl(mtd, (u8)((page_addr >> 16) & 0x0f), ctrl); /* A[xx:25] */
+#endif
+ /* Latch in address */
+ this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+
+ /*
+ * Wait a while for the data to be ready
+ */
+ if (this->dev_ready)
+ while (!this->dev_ready(mtd))
+ ;
+ else
+ CFG_NAND_READ_DELAY;
+
+ return 0;
+}
+#else
+/*
+ * NAND command for large page NAND devices (2k)
+ */
static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
{
struct nand_chip *this = mtd->priv;
+ int page_offs = offs;
int page_addr = page + block * CFG_NAND_PAGE_COUNT;
if (this->dev_ready)
else
CFG_NAND_READ_DELAY;
+ /* Emulate NAND_CMD_READOOB */
+ if (cmd == NAND_CMD_READOOB) {
+ page_offs += CFG_NAND_PAGE_SIZE;
+ cmd = NAND_CMD_READ0;
+ }
+
/* Begin command latch cycle */
this->hwcontrol(mtd, NAND_CTL_SETCLE);
this->write_byte(mtd, cmd);
this->hwcontrol(mtd, NAND_CTL_CLRCLE);
this->hwcontrol(mtd, NAND_CTL_SETALE);
/* Column address */
- this->write_byte(mtd, offs); /* A[7:0] */
- this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */
- this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */
-#ifdef CFG_NAND_4_ADDR_CYCLE
- /* One more address cycle for devices > 32MiB */
- this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */
+ this->write_byte(mtd, page_offs & 0xff); /* A[7:0] */
+ this->write_byte(mtd, (uchar)((page_offs >> 8) & 0xff)); /* A[11:9] */
+ /* Row address */
+ this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[19:12] */
+ this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[27:20] */
+#ifdef CFG_NAND_5_ADDR_CYCLE
+ /* One more address cycle for devices > 128MiB */
+ this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:28] */
#endif
/* Latch in address */
this->hwcontrol(mtd, NAND_CTL_CLRALE);
+ /* Begin command latch cycle */
+ this->hwcontrol(mtd, NAND_CTL_SETCLE);
+ /* Write out the start read command */
+ this->write_byte(mtd, NAND_CMD_READSTART);
+ /* End command latch cycle */
+ this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+
/*
* Wait a while for the data to be ready
*/
return 0;
}
+#endif
static int nand_is_bad_block(struct mtd_info *mtd, int block)
{
/*
* Read one byte
*/
- if (this->read_byte(mtd) != 0xff)
+ if (in_8(this->IO_ADDR_R) != 0xff)
return 1;
return 0;
oob_data = ecc_calc + 0x200;
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- this->enable_hwecc(mtd, NAND_ECC_READ);
+ this->ecc.hwctl(mtd, NAND_ECC_READ);
this->read_buf(mtd, p, eccsize);
- this->calculate_ecc(mtd, p, &ecc_calc[i]);
+ this->ecc.calculate(mtd, p, &ecc_calc[i]);
}
this->read_buf(mtd, oob_data, CFG_NAND_OOBSIZE);
* from correct_data(). We just hope that all possible errors
* are corrected by this routine.
*/
- stat = this->correct_data(mtd, p, &ecc_code[i], &ecc_calc[i]);
+ stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
}
return 0;
return 0;
}
+/*
+ * The main entry for NAND booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from NAND into SDRAM and starts it from there.
+ */
void nand_boot(void)
{
- ulong mem_size;
struct nand_chip nand_chip;
nand_info_t nand_info;
int ret;
- void (*uboot)(void);
-
- /*
- * Init sdram, so we have access to memory
- */
- mem_size = initdram(0);
+ __attribute__((noreturn)) void (*uboot)(void);
/*
* Init board specific nand support
/*
* Jump to U-Boot image
*/
- uboot = (void (*)(void))CFG_NAND_U_BOOT_START;
+ uboot = (void *)CFG_NAND_U_BOOT_START;
(*uboot)();
}
projects / karo-tx-uboot.git / blobdiff