X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farm926ejs%2Fmxs%2Fspl_power_init.c;h=6d6d416bcf00a07a2d2caae5823ba9dbc2d58ff4;hp=3d26b8d1b37525c924f96d7dd8e1056be19baab6;hb=69d8fb84dc7e53af358b85b99d2e852a0f64eb28;hpb=a1df6c3491e2810fc2c2ff88477421017cf7a159

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 3d26b8d1b3..6d6d416bcf 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -114,19 +114,16 @@ static void mxs_power_clock2pll(void)
 
 	debug("SPL: Switching CPU core clock source to PLL\n");
 
-	/*
-	 * TODO: Are we really? It looks like we turn on PLL0, but we then
-	 * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
-	 * set by mxs_power_clock2xtal()). Clearing this bit here seems to
-	 * introduce some instability (causing the CPU core to hang). Maybe
-	 * we aren't giving PLL0 enough time to stabilise?
-	 */
 	writel(CLKCTRL_PLL0CTRL0_POWER,
 		&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
-	udelay(100);
+	/*
+	 * The PLL is documented to lock within 10 µs from setting
+	 * the POWER bit.
+	 */
+	udelay(15);
 
 	/*
-	 * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
+	 * TODO: Should the PLL0 FORCE_LOCK bit be set here followed by a
 	 * wait on the PLL0 LOCK bit?
 	 */
 	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,