X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fmx5%2Flowlevel_init.S;h=6273b7aac8fdca72eb9dfc4b69af160e929082cc;hp=17a2bdbf1d267d25d652edc32c07ed6ba94c0691;hb=dfdb35946c027cdebf25c3705b2cce8658f71632;hpb=fbaa0493c14d5add2805ee8c889b06e14499193e

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 17a2bdbf1d..6273b7aac8 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -31,12 +31,12 @@
 
 	/* reconfigure L2 cache aux control reg */
 	ldr r0, =0xC0 |			/* tag RAM */ \
-	         0x4 |			/* data RAM */ \
-	         1 << 24 |		/* disable write allocate delay */ \
-	         1 << 23 |		/* disable write allocate combine */ \
-	         1 << 22		/* disable write allocate */
+		 0x4 |			/* data RAM */ \
+		 1 << 24 |		/* disable write allocate delay */ \
+		 1 << 23 |		/* disable write allocate combine */ \
+		 1 << 22		/* disable write allocate */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)
 	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10
 
@@ -45,6 +45,12 @@
 #endif
 
 	mcr 15, 1, r0, c9, c0, 2
+
+	/* enable L2 cache */
+	mrc 15, 0, r0, c1, c0, 1
+	orr r0, r0, #2
+	mcr 15, 0, r0, c1, c0, 1
+
 .endm /* init_l2cc */
 
 /* AIPS setup - Only setup MPROTx registers.
@@ -70,7 +76,7 @@
 
 /* M4IF setup */
 .macro init_m4if
-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51
 	/* VPU and IPU given higher priority (0x4)
 	 * IPU accesses with ID=0x1 given highest priority (=0xA)
 	 */
@@ -156,9 +162,8 @@ setup_pll_func:
 .endm
 
 .macro init_clock
-#if defined (CONFIG_MX51)
 	ldr r0, =CCM_BASE_ADDR
-
+#if defined (CONFIG_SOC_MX51)
 	/* Gate off clocks to the peripherals first */
 	ldr r1, =0x3FFFFFFF
 	str r1, [r0, #CLKCTL_CCGR0]
@@ -182,7 +187,7 @@ setup_pll_func:
 	str r1, [r0, #CLKCTL_CBCDR]
 	/* make sure divider effective */
 1:	ldr r1, [r0, #CLKCTL_CDHIPR]
-	cmp r1, #0x0
+	tst r1, #0x7f
 	bne 1b
 
 	/* Switch ARM to step clock */
@@ -193,7 +198,13 @@ setup_pll_func:
 	setup_pll PLL1_BASE_ADDR, 864
 	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
 #else
+#if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800
 	setup_pll PLL1_BASE_ADDR, 800
+#elif CONFIG_SYS_CPU_CLK == 600
+	setup_pll PLL1_BASE_ADDR, 600
+#else
+#error Unsupported CONFIG_SYS_CPU_CLK value
+#endif
 #endif
 
 	setup_pll PLL3_BASE_ADDR, 665
@@ -256,7 +267,7 @@ setup_pll_func:
 	str r1, [r0, #CLKCTL_CSCDR1]
 	/* make sure divider effective */
 1:	ldr r1, [r0, #CLKCTL_CDHIPR]
-	cmp r1, #0x0
+	tst r1, #0x7f
 	bne 1b
 
 	str r4, [r0, #CLKCTL_CCDR]
@@ -265,7 +276,7 @@ setup_pll_func:
 	mov r1, #0x000A0000
 	add r1, r1, #0x00000F0
 	str r1, [r0, #CLKCTL_CCOSR]
-#else	/* CONFIG_MX53 */
+#else	/* CONFIG_SOC_MX53 */
 	/* Gate off clocks to the peripherals first */
 	ldr r1, =0x3FFFFFFF
 	str r1, [r0, #CLKCTL_CCGR0]
@@ -284,21 +295,28 @@ setup_pll_func:
 	mov r1, #0x4
 	str r1, [r0, #CLKCTL_CCSR]
 
+#if !defined(CONFIG_SYS_CPU_CLK) || CONFIG_SYS_CPU_CLK == 800
 	setup_pll PLL1_BASE_ADDR, 800
+#elif CONFIG_SYS_CPU_CLK == 600
+	setup_pll PLL1_BASE_ADDR, 600
+#else
+#error Unsupported CONFIG_SYS_CPU_CLK value
+#endif
 
-        setup_pll PLL3_BASE_ADDR, 400
-
-        /* Switch peripheral to PLL3 */
-        ldr r1, =0x00015154
-        str r1, [r0, #CLKCTL_CBCMR]
-        ldr r1, =0x02898945
-        str r1, [r0, #CLKCTL_CBCDR]
-        /* make sure change is effective */
+	setup_pll PLL3_BASE_ADDR, 400
+#ifndef CONFIG_TX53
+	/* Switch peripheral to PLL3 */
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x00015154
+	str r1, [r0, #CLKCTL_CBCMR]
+	ldr r1, =0x02898945
+	str r1, [r0, #CLKCTL_CBCDR]
+	/* make sure change is effective */
 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
-        cmp r1, #0x0
-        bne 1b
+	tst r1, #0x7f
+	bne 1b
 
-        setup_pll PLL2_BASE_ADDR, 400
+	setup_pll PLL2_BASE_ADDR, 400
 
 	/* Switch peripheral to PLL2 */
 	ldr r1, =0x00888945
@@ -309,19 +327,57 @@ setup_pll_func:
 
 	/* change uart clk parent to pll2 */
 	ldr r1, [r0, #CLKCTL_CSCMR1]
-	and r1, r1, #0xfcffffff
-	orr r1, r1, #0x01000000
+	bic r1, #(0x3 << 24)
+	orr r1, r1, #(0x1 << 24)
 	str r1, [r0, #CLKCTL_CSCMR1]
 
 	/* make sure change is effective */
 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
-	cmp r1, #0x0
+	tst r1, #0x7f
 	bne 1b
 
-        setup_pll PLL3_BASE_ADDR, 216
+	setup_pll PLL3_BASE_ADDR, 216
 
 	setup_pll PLL4_BASE_ADDR, 455
 
+#else /* CONFIG_TX53 */
+	/* Switch peripheral to PLL 3 */
+	ldr r1, [r0, #CLKCTL_CBCMR]
+	bic r1, #(0x3 << 12)
+	orr r1, r1, #(1 << 12)
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	ldr r1, [r0, #CLKCTL_CBCDR]
+	orr r1, r1, #(1 << 25)
+	str r1, [r0, #CLKCTL_CBCDR]
+1:
+	/* make sure change is effective */
+	ldr r1, [r0, #CLKCTL_CDHIPR]
+	tst r1, #0x7f
+	bne 1b
+
+#if CONFIG_SYS_SDRAM_CLK == 533
+	setup_pll PLL2_BASE_ADDR, 533
+#elif CONFIG_SYS_SDRAM_CLK == 400
+	setup_pll PLL2_BASE_ADDR, 400
+#elif CONFIG_SYS_SDRAM_CLK == 333
+	setup_pll PLL2_BASE_ADDR, 333
+#else
+#error Unsupported CONFIG_SYS_SDRAM_CLK
+#endif
+
+	/* Switch peripheral to PLL2 */
+	ldr r1, [r0, #CLKCTL_CBCDR]
+	bic r1, #(1 << 25)
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	ldr r1, [r0, #CLKCTL_CBCMR]
+	bic r1, #(3 << 12)
+	orr r1, #(2 << 12)
+	str r1, [r0, #CLKCTL_CBCMR]
+#endif
+        setup_pll PLL3_BASE_ADDR, 216
+
 	/* Set the platform clock dividers */
 	ldr r0, =ARM_BASE_ADDR
 	ldr r1, =0x00000124
@@ -337,9 +393,13 @@ setup_pll_func:
 
 	/* make uart div=6 */
 	ldr r1, [r0, #CLKCTL_CSCDR1]
-	and r1, r1, #0xffffffc0
+	bic r1, #(0x3f << 0)
 	orr r1, r1, #0x0a
 	str r1, [r0, #CLKCTL_CSCDR1]
+	/* make sure divider effective */
+1:	ldr r1, [r0, #CLKCTL_CDHIPR]
+	tst r1, #0x7f
+	bne 1b
 
 	/* Restore the default values in the Gate registers */
 	ldr r1, =0xFFFFFFFF
@@ -352,21 +412,15 @@ setup_pll_func:
 	str r1, [r0, #CLKCTL_CCGR6]
 	str r1, [r0, #CLKCTL_CCGR7]
 
-        mov r1, #0x00000
-        str r1, [r0, #CLKCTL_CCDR]
-
-        /* for cko - for ARM div by 8 */
-        mov r1, #0x000A0000
-        add r1, r1, #0x00000F0
-        str r1, [r0, #CLKCTL_CCOSR]
+	mov r1, #0x00000
+	str r1, [r0, #CLKCTL_CCDR]
 
-#endif	/* CONFIG_MX53 */
-.endm
+	/* for cko - for ARM div by 8 */
+	mov r1, #0x000A0000
+	add r1, r1, #0x00000F0
+	str r1, [r0, #CLKCTL_CCOSR]
 
-.macro setup_wdog
-	ldr r0, =WDOG1_BASE_ADDR
-	mov r1, #0x30
-	strh r1, [r0]
+#endif	/* CONFIG_SOC_MX53 */
 .endm
 
 ENTRY(lowlevel_init)
@@ -407,10 +461,13 @@ W_DP_800:		.word DP_OP_800
 			.word DP_MFD_800
 			.word DP_MFN_800
 #endif
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)
 W_DP_665:		.word DP_OP_665
 			.word DP_MFD_665
 			.word DP_MFN_665
+W_DP_600:		.word DP_OP_600
+			.word DP_MFD_600
+			.word DP_MFN_600
 #endif
 W_DP_216:		.word DP_OP_216
 			.word DP_MFD_216
@@ -421,3 +478,6 @@ W_DP_400:               .word DP_OP_400
 W_DP_455:               .word DP_OP_455
 			.word DP_MFD_455
 			.word DP_MFN_455
+W_DP_533:		.word DP_OP_533
+			.word DP_MFD_533
+			.word DP_MFN_533